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Improve handling of datalayout for generic targets.

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Flag 32-bit vector types as only requiring 32-bit alignment (preemptive
bug fix for 32xi1 vectors).

Force module datalayouts to be the same before linking them to silence
an LLVM warning.

Finishes issue #309.
This commit is contained in:
Matt Pharr
2012-07-06 12:51:17 -07:00
parent 8defbeb248
commit b363b98211
3 changed files with 15 additions and 3 deletions
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8
builtins.cpp
View File

@@ -619,6 +619,14 @@ AddBitcodeToModule(const unsigned char *bitcode, int length,
mTriple.getVendor() == bcTriple.getVendor());
bcModule->setTargetTriple(mTriple.str());
// This is also suboptimal; LLVM issues a warning about linking
// modules with different datalayouts, due to things like
// bulitins-c.c having the regular IA layout, but the generic
// targets having a layout with 16-bit alignment for 16xi1 vectors.
// As long as builtins-c.c doesn't have any 16xi1 vector types
// (which it shouldn't!), then this override is safe.
bcModule->setDataLayout(module->getDataLayout());
std::string(linkError);
if (llvm::Linker::LinkModules(module, bcModule,
llvm::Linker::DestroySource,

2
builtins/target-generic-common.ll
View File

@@ -29,6 +29,8 @@
;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128-v16:16:16-v32:32:32";
define(`MASK',`i1')
include(`util.m4')

8
module.cpp
View File

@@ -241,9 +241,11 @@ Module::Module(const char *fn) {
module->setTargetTriple(g->target.GetTripleString());
if (g->target.isa == Target::GENERIC) {
// <16 x i1> vectors only need 16 bit / 2 byte alignment
std::string datalayout = module->getDataLayout();
datalayout += "v16:16:16";
// <16 x i1> vectors only need 16 bit / 2 byte alignment, so add
// that to the regular datalayout string for IA..
std::string datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
"i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-"
"f80:128:128-n8:16:32:64-S128-v16:16:16-v32:32:32";
module->setDataLayout(datalayout);
}