target-[sse4|avx]_common.ll are twin brothers, which diffes only cosmetically. This commit makes them diffable. No real changes, except adding alwaysinline to sse version iof __max_uniform_int32/__max_uniform_uint32
This commit is contained in:
Dmitry Babokin
@@ -1,4 +1,4 @@
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;; Copyright (c) 2010-2011, Intel Corporation
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;; Copyright (c) 2010-2013, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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@@ -37,24 +37,6 @@ define_prefetches()
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define_shuffles()
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aossoa()
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; uniform float iv = extract(__rcp_u(v), 0);
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; return iv * (2. - v * iv);
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%vecval = insertelement <4 x float> undef, float %0, i32 0
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%call = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecval)
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%scall = extractelement <4 x float> %call, i32 0
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; do one N-R iteration
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%v_iv = fmul float %0, %scall
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%two_minus = fsub float 2., %v_iv
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%iv_mul = fmul float %scall, %two_minus
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ret float %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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@@ -77,7 +59,8 @@ define float @__round_uniform_float(float) nounwind readonly alwaysinline {
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; r3 = a3
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;
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; It doesn't matter what we pass as a, since we only need the r0 value
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; here. So we pass the same register for both.
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; here. So we pass the same register for both. Further, only the 0th
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; element of the b parameter matters
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%xi = insertelement <4 x float> undef, float %0, i32 0
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 8)
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%rs = extractelement <4 x float> %xr, i32 0
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@@ -117,7 +100,7 @@ define double @__round_uniform_double(double) nounwind readonly alwaysinline {
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define double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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; roundsd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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@@ -126,12 +109,31 @@ define double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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define double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundpd, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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; roundsd, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; do the rcpss call
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; uniform float iv = extract(__rcp_u(v), 0);
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; return iv * (2. - v * iv);
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%vecval = insertelement <4 x float> undef, float %0, i32 0
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%call = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecval)
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%scall = extractelement <4 x float> %call, i32 0
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; do one N-R iteration to improve precision, as above
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%v_iv = fmul float %0, %scall
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%two_minus = fsub float 2., %v_iv
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%iv_mul = fmul float %scall, %two_minus
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ret float %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rsqrt
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@@ -144,6 +146,7 @@ define float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
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%vis = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %v)
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%is = extractelement <4 x float> %vis, i32 0
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul float %0, %is
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%v_is_is = fmul float %v_is, %is
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@@ -164,9 +167,18 @@ define float @__sqrt_uniform_float(float) nounwind readonly alwaysinline {
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define double @__sqrt_uniform_double(double) nounwind alwaysinline {
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sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; fastmath
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;; fast math mode
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declare void @llvm.x86.sse.stmxcsr(i8 *) nounwind
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declare void @llvm.x86.sse.ldmxcsr(i8 *) nounwind
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@@ -200,6 +212,22 @@ define float @__min_uniform_float(float, float) nounwind readonly alwaysinline {
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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define double @__min_uniform_double(double, double) nounwind readnone alwaysinline {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.min.sd, %0, %1)
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ret double %ret
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}
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define double @__max_uniform_double(double, double) nounwind readnone alwaysinline {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.max.sd, %0, %1)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int min/max
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@@ -235,7 +263,7 @@ define i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops
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;; horizontal ops / reductions
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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@@ -251,32 +279,6 @@ define i64 @__popcnt_int64(i64) nounwind readonly alwaysinline {
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ret i64 %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define double @__sqrt_uniform_double(double) nounwind alwaysinline {
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sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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define double @__min_uniform_double(double, double) nounwind readnone alwaysinline {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.min.sd, %0, %1)
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ret double %ret
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}
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define double @__max_uniform_double(double, double) nounwind readnone alwaysinline {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.max.sd, %0, %1)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int8/int16 builtins
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@@ -1,4 +1,4 @@
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;; Copyright (c) 2010-2011, Intel Corporation
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;; Copyright (c) 2010-2013, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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@@ -29,6 +29,9 @@
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; SSE4 target implementation.
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ctlztz()
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define_prefetches()
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define_shuffles()
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@@ -67,7 +70,7 @@ define float @__round_uniform_float(float) nounwind readonly alwaysinline {
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define float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round down 0b01 | don't signal precision exceptions 0b1010 = 9
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; roundps, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 9)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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@@ -97,7 +100,7 @@ define double @__round_uniform_double(double) nounwind readonly alwaysinline {
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define double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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; roundsd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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@@ -106,7 +109,7 @@ define double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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define double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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; roundsd, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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@@ -119,6 +122,8 @@ declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; do the rcpss call
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; uniform float iv = extract(__rcp_u(v), 0);
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; return iv * (2. - v * iv);
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%vecval = insertelement <4 x float> undef, float %0, i32 0
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%call = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecval)
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%scall = extractelement <4 x float> %call, i32 0
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@@ -130,9 +135,8 @@ define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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ret float %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; rsqrt
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;; rsqrt
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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@@ -154,7 +158,7 @@ define float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; sqrt
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;; sqrt
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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@@ -163,6 +167,16 @@ define float @__sqrt_uniform_float(float) nounwind readonly alwaysinline {
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define double @__sqrt_uniform_double(double) nounwind alwaysinline {
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sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; fast math mode
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@@ -198,36 +212,25 @@ define float @__min_uniform_float(float, float) nounwind readonly alwaysinline {
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define double @__sqrt_uniform_double(double) nounwind alwaysinline {
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sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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define double @__min_uniform_double(double, double) nounwind readnone {
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define double @__min_uniform_double(double, double) nounwind readnone alwaysinline {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.min.sd, %0, %1)
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ret double %ret
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}
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define double @__max_uniform_double(double, double) nounwind readnone {
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define double @__max_uniform_double(double, double) nounwind readnone alwaysinline {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.max.sd, %0, %1)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 min/max
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;; int min/max
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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@@ -242,8 +245,9 @@ define i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; unsigned int min/max
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;; unsigned int min/max
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declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
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@@ -258,9 +262,8 @@ define i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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;; horizontal ops / reductions
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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