Add SSE4-16 target.
Along the lines of sse4-8, this is an 8-wide target for SSE4, using 16-bit elements for the mask. It's thus (in principle) the best target for SIMD computation with 16-bit datatypes.
This commit is contained in:
Matt Pharr
2
Makefile
2
Makefile
@@ -123,7 +123,7 @@ CXX_SRC=ast.cpp builtins.cpp cbackend.cpp ctx.cpp decl.cpp expr.cpp func.cpp \
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HEADERS=ast.h builtins.h ctx.h decl.h expr.h func.h ispc.h llvmutil.h module.h \
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opt.h stmt.h sym.h type.h util.h
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TARGETS=neon avx1 avx1-x2 avx11 avx11-x2 avx2 avx2-x2 sse2 sse2-x2 sse4 sse4-x2 \
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sse4-8 generic-4 generic-8 generic-16 generic-32 generic-64 generic-1
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sse4-8 sse4-16 generic-4 generic-8 generic-16 generic-32 generic-64 generic-1
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# These files need to be compiled in two versions - 32 and 64 bits.
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BUILTINS_SRC_TARGET=$(addprefix builtins/target-, $(addsuffix .ll, $(TARGETS)))
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# These are files to be compiled in single version.
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16
builtins.cpp
16
builtins.cpp
@@ -862,10 +862,22 @@ DefineStdlib(SymbolTable *symbolTable, llvm::LLVMContext *ctx, llvm::Module *mod
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break;
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case 8:
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if (runtime32) {
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EXPORT_MODULE(builtins_bitcode_sse4_x2_32bit);
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if (g->target->getMaskBitCount() == 16) {
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EXPORT_MODULE(builtins_bitcode_sse4_16_32bit);
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}
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else {
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Assert(g->target->getMaskBitCount() == 32);
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EXPORT_MODULE(builtins_bitcode_sse4_x2_32bit);
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}
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}
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else {
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EXPORT_MODULE(builtins_bitcode_sse4_x2_64bit);
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if (g->target->getMaskBitCount() == 16) {
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EXPORT_MODULE(builtins_bitcode_sse4_16_64bit);
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}
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else {
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Assert(g->target->getMaskBitCount() == 32);
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EXPORT_MODULE(builtins_bitcode_sse4_x2_64bit);
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}
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}
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break;
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case 16:
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436
builtins/target-sse4-16.ll
Normal file
436
builtins/target-sse4-16.ll
Normal file
@@ -0,0 +1,436 @@
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;; Copyright (c) 2013, Google, Inc.
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Google, Inc. nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Define common 4-wide stuff
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define(`WIDTH',`8')
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define(`MASK',`i16')
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include(`util.m4')
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stdlib_core()
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packed_load_and_store()
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scans()
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int64minmax()
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include(`target-sse4-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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declare float @__half_to_float_uniform(i16 %v) nounwind readnone
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declare <WIDTH x float> @__half_to_float_varying(<WIDTH x i16> %v) nounwind readnone
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declare i16 @__float_to_half_uniform(float %v) nounwind readnone
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declare <WIDTH x i16> @__float_to_half_varying(<WIDTH x float> %v) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
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define <WIDTH x float> @__rcp_varying_float(<WIDTH x float>) nounwind readonly alwaysinline {
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unary4to8(call, float, @llvm.x86.sse.rcp.ps, %0)
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; do one N-R iteration to improve precision
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; float iv = __rcp_v(v);
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; return iv * (2. - v * iv);
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%v_iv = fmul <8 x float> %0, %call
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%two_minus = fsub <8 x float> <float 2., float 2., float 2., float 2.,
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float 2., float 2., float 2., float 2.>, %v_iv
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%iv_mul = fmul <8 x float> %call, %two_minus
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ret <8 x float> %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; rsqrt
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declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
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define <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %v) nounwind readonly alwaysinline {
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; float is = __rsqrt_v(v);
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unary4to8(is, float, @llvm.x86.sse.rsqrt.ps, %v)
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul <8 x float> %v, %is
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%v_is_is = fmul <8 x float> %v_is, %is
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%three_sub = fsub <8 x float> <float 3., float 3., float 3., float 3.,
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float 3., float 3., float 3., float 3.>, %v_is_is
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%is_mul = fmul <8 x float> %is, %three_sub
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%half_scale = fmul <8 x float> <float 0.5, float 0.5, float 0.5, float 0.5,
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float 0.5, float 0.5, float 0.5, float 0.5>, %is_mul
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ret <8 x float> %half_scale
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; sqrt
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declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
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define <8 x float> @__sqrt_varying_float(<8 x float>) nounwind readonly alwaysinline {
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unary4to8(call, float, @llvm.x86.sse.sqrt.ps, %0)
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ret <8 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
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define <8 x double> @__sqrt_varying_double(<8 x double>) nounwind
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alwaysinline {
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unary2to8(ret, double, @llvm.x86.sse2.sqrt.pd, %0)
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ret <8 x double> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
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define <8 x float> @__round_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; roundps, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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round4to8(%0, 8)
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}
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define <8 x float> @__floor_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; roundps, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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round4to8(%0, 9)
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}
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define <8 x float> @__ceil_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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round4to8(%0, 10)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
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define <8 x double> @__round_varying_double(<8 x double>) nounwind readonly alwaysinline {
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round2to8double(%0, 8)
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}
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define <8 x double> @__floor_varying_double(<8 x double>) nounwind readonly alwaysinline {
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round2to8double(%0, 9)
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}
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define <8 x double> @__ceil_varying_double(<8 x double>) nounwind readonly alwaysinline {
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round2to8double(%0, 10)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
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define <8 x float> @__max_varying_float(<8 x float>, <8 x float>) nounwind readonly alwaysinline {
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binary4to8(call, float, @llvm.x86.sse.max.ps, %0, %1)
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ret <8 x float> %call
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}
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define <8 x float> @__min_varying_float(<8 x float>, <8 x float>) nounwind readonly alwaysinline {
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binary4to8(call, float, @llvm.x86.sse.min.ps, %0, %1)
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ret <8 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 min/max
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define <8 x i32> @__min_varying_int32(<8 x i32>, <8 x i32>) nounwind readonly alwaysinline {
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binary4to8(call, i32, @llvm.x86.sse41.pminsd, %0, %1)
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ret <8 x i32> %call
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}
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define <8 x i32> @__max_varying_int32(<8 x i32>, <8 x i32>) nounwind readonly alwaysinline {
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binary4to8(call, i32, @llvm.x86.sse41.pmaxsd, %0, %1)
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ret <8 x i32> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; unsigned int min/max
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define <8 x i32> @__min_varying_uint32(<8 x i32>, <8 x i32>) nounwind readonly alwaysinline {
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binary4to8(call, i32, @llvm.x86.sse41.pminud, %0, %1)
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ret <8 x i32> %call
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}
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define <8 x i32> @__max_varying_uint32(<8 x i32>, <8 x i32>) nounwind readonly alwaysinline {
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binary4to8(call, i32, @llvm.x86.sse41.pmaxud, %0, %1)
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ret <8 x i32> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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define <8 x double> @__min_varying_double(<8 x double>, <8 x double>) nounwind readnone {
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binary2to8(ret, double, @llvm.x86.sse2.min.pd, %0, %1)
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ret <8 x double> %ret
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}
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define <8 x double> @__max_varying_double(<8 x double>, <8 x double>) nounwind readnone {
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binary2to8(ret, double, @llvm.x86.sse2.max.pd, %0, %1)
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ret <8 x double> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; svml
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; FIXME
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declare <8 x float> @__svml_sin(<8 x float>)
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declare <8 x float> @__svml_cos(<8 x float>)
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declare void @__svml_sincos(<8 x float>, <8 x float> *, <8 x float> *)
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declare <8 x float> @__svml_tan(<8 x float>)
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declare <8 x float> @__svml_atan(<8 x float>)
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declare <8 x float> @__svml_atan2(<8 x float>, <8 x float>)
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declare <8 x float> @__svml_exp(<8 x float>)
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declare <8 x float> @__svml_log(<8 x float>)
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declare <8 x float> @__svml_pow(<8 x float>, <8 x float>)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone
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define i64 @__movmsk(<8 x MASK>) nounwind readnone alwaysinline {
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%m8 = trunc <8 x MASK> %0 to <8 x i8>
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%mask8 = shufflevector <8 x i8> %m8, <8 x i8> zeroinitializer,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
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%m = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %mask8)
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%m64 = zext i32 %m to i64
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ret i64 %m64
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}
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define i1 @__any(<8 x MASK>) nounwind readnone alwaysinline {
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%m = call i64 @__movmsk(<8 x MASK> %0)
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%mne = icmp ne i64 %m, 0
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ret i1 %mne
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}
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define i1 @__all(<8 x MASK>) nounwind readnone alwaysinline {
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%m = call i64 @__movmsk(<8 x MASK> %0)
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%meq = icmp eq i64 %m, ALL_ON_MASK
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ret i1 %meq
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}
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define i1 @__none(<8 x MASK>) nounwind readnone alwaysinline {
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%m = call i64 @__movmsk(<8 x MASK> %0)
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%meq = icmp eq i64 %m, 0
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ret i1 %meq
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}
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define internal <8 x float> @__add_varying_float(<8 x float>, <8 x float>) {
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%r = fadd <8 x float> %0, %1
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ret <8 x float> %r
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}
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define internal float @__add_uniform_float(float, float) {
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%r = fadd float %0, %1
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ret float %r
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}
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define float @__reduce_add_float(<8 x float>) nounwind readonly alwaysinline {
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reduce8(float, @__add_varying_float, @__add_uniform_float)
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}
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define float @__reduce_min_float(<8 x float>) nounwind readnone {
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reduce8(float, @__min_varying_float, @__min_uniform_float)
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}
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define float @__reduce_max_float(<8 x float>) nounwind readnone {
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reduce8(float, @__max_varying_float, @__max_uniform_float)
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}
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define internal <8 x i32> @__add_varying_int32(<8 x i32>, <8 x i32>) {
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%r = add <8 x i32> %0, %1
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ret <8 x i32> %r
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}
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define internal i32 @__add_uniform_int32(i32, i32) {
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%r = add i32 %0, %1
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ret i32 %r
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}
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define i32 @__reduce_add_int32(<8 x i32>) nounwind readnone {
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reduce8(i32, @__add_varying_int32, @__add_uniform_int32)
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}
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define i32 @__reduce_min_int32(<8 x i32>) nounwind readnone {
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reduce8(i32, @__min_varying_int32, @__min_uniform_int32)
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}
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define i32 @__reduce_max_int32(<8 x i32>) nounwind readnone {
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reduce8(i32, @__max_varying_int32, @__max_uniform_int32)
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}
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define i32 @__reduce_min_uint32(<8 x i32>) nounwind readnone {
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reduce8(i32, @__min_varying_uint32, @__min_uniform_uint32)
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}
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define i32 @__reduce_max_uint32(<8 x i32>) nounwind readnone {
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reduce8(i32, @__max_varying_uint32, @__max_uniform_uint32)
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}
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define internal <8 x double> @__add_varying_double(<8 x double>, <8 x double>) {
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%r = fadd <8 x double> %0, %1
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ret <8 x double> %r
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}
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define internal double @__add_uniform_double(double, double) {
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%r = fadd double %0, %1
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ret double %r
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}
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define double @__reduce_add_double(<8 x double>) nounwind readnone {
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reduce8(double, @__add_varying_double, @__add_uniform_double)
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}
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define double @__reduce_min_double(<8 x double>) nounwind readnone {
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reduce8(double, @__min_varying_double, @__min_uniform_double)
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}
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define double @__reduce_max_double(<8 x double>) nounwind readnone {
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reduce8(double, @__max_varying_double, @__max_uniform_double)
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}
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define internal <8 x i64> @__add_varying_int64(<8 x i64>, <8 x i64>) {
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%r = add <8 x i64> %0, %1
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ret <8 x i64> %r
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}
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||||
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||||
define internal i64 @__add_uniform_int64(i64, i64) {
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%r = add i64 %0, %1
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ret i64 %r
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}
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||||
|
||||
define i64 @__reduce_add_int64(<8 x i64>) nounwind readnone {
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reduce8(i64, @__add_varying_int64, @__add_uniform_int64)
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}
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||||
|
||||
define i64 @__reduce_min_int64(<8 x i64>) nounwind readnone {
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reduce8(i64, @__min_varying_int64, @__min_uniform_int64)
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}
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||||
|
||||
define i64 @__reduce_max_int64(<8 x i64>) nounwind readnone {
|
||||
reduce8(i64, @__max_varying_int64, @__max_uniform_int64)
|
||||
}
|
||||
|
||||
define i64 @__reduce_min_uint64(<8 x i64>) nounwind readnone {
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||||
reduce8(i64, @__min_varying_uint64, @__min_uniform_uint64)
|
||||
}
|
||||
|
||||
define i64 @__reduce_max_uint64(<8 x i64>) nounwind readnone {
|
||||
reduce8(i64, @__max_varying_uint64, @__max_uniform_uint64)
|
||||
}
|
||||
|
||||
reduce_equal(8)
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; masked store
|
||||
|
||||
define void @__masked_store_blend_i64(<8 x i64>* nocapture, <8 x i64>,
|
||||
<8 x MASK> %mask) nounwind
|
||||
alwaysinline {
|
||||
%mask_as_i1 = trunc <8 x MASK> %mask to <8 x i1>
|
||||
%old = load <8 x i64>* %0, align 4
|
||||
%blend = select <8 x i1> %mask_as_i1, <8 x i64> %1, <8 x i64> %old
|
||||
store <8 x i64> %blend, <8 x i64>* %0, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @__masked_store_blend_i32(<8 x i32>* nocapture, <8 x i32>,
|
||||
<8 x MASK> %mask) nounwind alwaysinline {
|
||||
%mask_as_i1 = trunc <8 x MASK> %mask to <8 x i1>
|
||||
%old = load <8 x i32>* %0, align 4
|
||||
%blend = select <8 x i1> %mask_as_i1, <8 x i32> %1, <8 x i32> %old
|
||||
store <8 x i32> %blend, <8 x i32>* %0, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @__masked_store_blend_i16(<8 x i16>* nocapture, <8 x i16>,
|
||||
<8 x MASK> %mask) nounwind alwaysinline {
|
||||
%mask_as_i1 = trunc <8 x MASK> %mask to <8 x i1>
|
||||
%old = load <8 x i16>* %0, align 4
|
||||
%blend = select <8 x i1> %mask_as_i1, <8 x i16> %1, <8 x i16> %old
|
||||
store <8 x i16> %blend, <8 x i16>* %0, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @__masked_store_blend_i8(<8 x i8>* nocapture, <8 x i8>,
|
||||
<8 x MASK> %mask) nounwind alwaysinline {
|
||||
%mask_as_i1 = trunc <8 x MASK> %mask to <8 x i1>
|
||||
%old = load <8 x i8>* %0, align 4
|
||||
%blend = select <8 x i1> %mask_as_i1, <8 x i8> %1, <8 x i8> %old
|
||||
store <8 x i8> %blend, <8 x i8>* %0, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
gen_masked_store(i8)
|
||||
gen_masked_store(i16)
|
||||
gen_masked_store(i32)
|
||||
gen_masked_store(i64)
|
||||
|
||||
masked_store_float_double()
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; unaligned loads/loads+broadcasts
|
||||
|
||||
masked_load(i8, 1)
|
||||
masked_load(i16, 2)
|
||||
masked_load(i32, 4)
|
||||
masked_load(float, 4)
|
||||
masked_load(i64, 8)
|
||||
masked_load(double, 8)
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; gather/scatter
|
||||
|
||||
; define these with the macros from stdlib.m4
|
||||
|
||||
gen_gather_factored(i8)
|
||||
gen_gather_factored(i16)
|
||||
gen_gather_factored(i32)
|
||||
gen_gather_factored(float)
|
||||
gen_gather_factored(i64)
|
||||
gen_gather_factored(double)
|
||||
|
||||
gen_scatter(i8)
|
||||
gen_scatter(i16)
|
||||
gen_scatter(i32)
|
||||
gen_scatter(float)
|
||||
gen_scatter(i64)
|
||||
gen_scatter(double)
|
||||
14
ispc.cpp
14
ispc.cpp
@@ -318,6 +318,14 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) :
|
||||
this->m_maskingIsFree = false;
|
||||
this->m_maskBitCount = 8;
|
||||
}
|
||||
else if (!strcasecmp(isa, "sse4-16")) {
|
||||
this->m_isa = Target::SSE4;
|
||||
this->m_nativeVectorWidth = 8;
|
||||
this->m_vectorWidth = 8;
|
||||
this->m_attributes = "+sse,+sse2,+sse3,+sse41,-sse42,-sse4a,+ssse3,-popcnt,+cmov";
|
||||
this->m_maskingIsFree = false;
|
||||
this->m_maskBitCount = 16;
|
||||
}
|
||||
else if (!strcasecmp(isa, "generic-4")) {
|
||||
this->m_isa = Target::GENERIC;
|
||||
this->m_nativeVectorWidth = 4;
|
||||
@@ -575,9 +583,9 @@ Target::SupportedTargetArchs() {
|
||||
|
||||
const char *
|
||||
Target::SupportedTargetISAs() {
|
||||
return "neon, sse2, sse2-x2, sse4, sse4-x2, avx, avx-x2"
|
||||
", avx1.1, avx1.1-x2, avx2, avx2-x2"
|
||||
", generic-1, generic-4, generic-8, generic-16, generic-32";
|
||||
return "neon, sse2, sse2-x2, sse4, sse4-8, sse4-16, sse4-x2, "
|
||||
"avx, avx-x2, avx1.1, avx1.1-x2, avx2, avx2-x2,"
|
||||
"generic-1, generic-4, generic-8, generic-16, generic-32";
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -37,7 +37,7 @@ parser.add_option("-g", "--generics-include", dest="include_file", help="Filenam
|
||||
parser.add_option("-f", "--ispc-flags", dest="ispc_flags", help="Additional flags for ispc (-g, -O1, ...)",
|
||||
default="")
|
||||
parser.add_option('-t', '--target', dest='target',
|
||||
help='Set compilation target (neon, sse2, sse2-x2, sse4, sse4-x2, sse4-8, avx, avx-x2, generic-4, generic-8, generic-16, generic-32)',
|
||||
help='Set compilation target (neon, sse2, sse2-x2, sse4, sse4-x2, sse4-8, sse4-16, avx, avx-x2, generic-4, generic-8, generic-16, generic-32)',
|
||||
default="sse4")
|
||||
parser.add_option('-a', '--arch', dest='arch',
|
||||
help='Set architecture (arm, x86, x86-64)',
|
||||
|
||||
Reference in New Issue
Block a user