a+1
This commit is contained in:
Evghenii
@@ -9,6 +9,7 @@ packed_load_and_store()
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scans()
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int64minmax()
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aossoa()
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rdrand_decls()
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
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@@ -652,121 +653,10 @@ define <1 x float> @__rsqrt_varying_float(<1 x float> %v) nounwind readonly alw
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; svml stuff
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declare <1 x float> @__svml_sind(<1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_asind(<1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_cosd(<1 x float>) nounwind readnone alwaysinline
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declare void @__svml_sincosd(<1 x float>, <1 x float> *, <1 x float> *) nounwind readnone alwaysinline
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declare <1 x float> @__svml_tand(<1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_atand(<1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_atan2d(<1 x float>, <1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_expd(<1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_logd(<1 x float>) nounwind readnone alwaysinline
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declare <1 x float> @__svml_powd(<1 x float>, <1 x float>) nounwind readnone alwaysinline
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include(`svml.m4')
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svml_stubs(float,f,WIDTH)
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svml_stubs(double,d,WIDTH)
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define <1 x float> @__svml_sinf(<1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_sinf4(<1 x float> %0)
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;ret <1 x float> %ret
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;%r = extractelement <1 x float> %0, i32 0
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;%s = call float @llvm.sin.f32(float %r)
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;%rv = insertelement <1 x float> undef, float %r, i32 0
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;ret <1 x float> %rv
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unary1to1(float,@llvm.sin.f32)
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}
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define <1 x float> @__svml_asinf(<1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_asinf4(<1 x float> %0)
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;ret <1 x float> %ret
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;%r = extractelement <1 x float> %0, i32 0
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;%s = call float @llvm.asin.f32(float %r)
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;%rv = insertelement <1 x float> undef, float %r, i32 0
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;ret <1 x float> %rv
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unary1to1(float,@llvm.asin.f32)
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}
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define <1 x float> @__svml_cosf(<1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_cosf4(<1 x float> %0)
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;ret <1 x float> %ret
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;%r = extractelement <1 x float> %0, i32 0
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;%s = call float @llvm.cos.f32(float %r)
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;%rv = insertelement <1 x float> undef, float %r, i32 0
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;ret <1 x float> %rv
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unary1to1(float, @llvm.cos.f32)
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}
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define void @__svml_sincosf(<1 x float>, <1 x float> *, <1 x float> *) nounwind readnone alwaysinline {
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; %s = call <1 x float> @__svml_sincosf4(<1 x float> * %2, <1 x float> %0)
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; store <1 x float> %s, <1 x float> * %1
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; ret void
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%sin = call <1 x float> @__svml_sinf(<1 x float> %0)
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%cos = call <1 x float> @__svml_cosf(<1 x float> %0)
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store <1 x float> %sin, <1 x float> * %1
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store <1 x float> %cos, <1 x float> * %2
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ret void
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}
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define <1 x float> @__svml_tanf(<1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_tanf4(<1 x float> %0)
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;ret <1 x float> %ret
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;%r = extractelement <1 x float> %0, i32 0
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;%s = call float @llvm_tan_f32(float %r)
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;%rv = insertelement <1 x float> undef, float %r, i32 0
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;ret <1 x float> %rv
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;unasry1to1(float, @llvm.tan.f32)
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; UNSUPPORTED!
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ret <1 x float > %0
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}
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define <1 x float> @__svml_atanf(<1 x float>) nounwind readnone alwaysinline {
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; %ret = call <1 x float> @__svml_atanf4(<1 x float> %0)
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; ret <1 x float> %ret
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;%r = extractelement <1 x float> %0, i32 0
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;%s = call float @llvm_atan_f32(float %r)
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;%rv = insertelement <1 x float> undef, float %r, i32 0
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;ret <1 x float> %rv
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;unsary1to1(float,@llvm.atan.f32)
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;UNSUPPORTED!
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ret <1 x float > %0
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}
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define <1 x float> @__svml_atan2f(<1 x float>, <1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_atan2f4(<1 x float> %0, <1 x float> %1)
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;ret <1 x float> %ret
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;%y = extractelement <1 x float> %0, i32 0
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;%x = extractelement <1 x float> %1, i32 0
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;%q = fdiv float %y, %x
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;%a = call float @llvm.atan.f32 (float %q)
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;%rv = insertelement <1 x float> undef, float %a, i32 0
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;ret <1 x float> %rv
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; UNSUPPORTED!
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ret <1 x float > %0
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}
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define <1 x float> @__svml_expf(<1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_expf4(<1 x float> %0)
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;ret <1 x float> %ret
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unary1to1(float, @llvm.exp.f32)
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}
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define <1 x float> @__svml_logf(<1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_logf4(<1 x float> %0)
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;ret <1 x float> %ret
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unary1to1(float, @llvm.log.f32)
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}
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define <1 x float> @__svml_powf(<1 x float>, <1 x float>) nounwind readnone alwaysinline {
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;%ret = call <1 x float> @__svml_powf4(<1 x float> %0, <1 x float> %1)
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;ret <1 x float> %ret
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%r = extractelement <1 x float> %0, i32 0
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%e = extractelement <1 x float> %1, i32 0
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%s = call float @llvm.pow.f32(float %r,float %e)
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%rv = insertelement <1 x float> undef, float %s, i32 0
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ret <1 x float> %rv
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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@@ -991,3 +881,14 @@ declare <WIDTH x i16> @__float_to_half_varying(<WIDTH x float> %v) nounwind read
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define_avgs()
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;;;;;;; nvptx64
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declare i32 @__tid_x() nounwind readnone alwaysinline
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declare i32 @__warpsize() nounwind readnone alwaysinline
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declare i32 @__ctaid_x() nounwind readnone alwaysinline
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declare i32 @__ctaid_y() nounwind readnone alwaysinline
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declare i32 @__ctaid_z() nounwind readnone alwaysinline
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declare i32 @__nctaid_x() nounwind readnone alwaysinline
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declare i32 @__nctaid_y() nounwind readnone alwaysinline
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declare i32 @__nctaid_z() nounwind readnone alwaysinline
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@@ -386,3 +386,14 @@ declare void @__prefetch_read_uniform_nt(i8 * nocapture) nounwind
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define_avgs()
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;;;;;;; nvptx64
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declare i32 @__tid_x() nounwind readnone alwaysinline
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declare i32 @__warpsize() nounwind readnone alwaysinline
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declare i32 @__ctaid_x() nounwind readnone alwaysinline
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declare i32 @__ctaid_y() nounwind readnone alwaysinline
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declare i32 @__ctaid_z() nounwind readnone alwaysinline
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declare i32 @__nctaid_x() nounwind readnone alwaysinline
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declare i32 @__nctaid_y() nounwind readnone alwaysinline
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declare i32 @__nctaid_z() nounwind readnone alwaysinline
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