590 lines
22 KiB
LLVM
590 lines
22 KiB
LLVM
;; Copyright (c) 2010-2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; *** Untested *** AVX target implementation.
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;;
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;; The LLVM AVX code generator is incomplete, so the ispc AVX target
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;; hasn't yet been tested. There is therefore a higher-than-normal
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;; chance that there are bugs in the code in this file.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Basic 8-wide definitions
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stdlib_core(8)
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packed_load_and_store(8)
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int8_16(8)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <8 x float> @llvm.x86.avx.rcp.ps(<8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.rcp.ss(<8 x float>) nounwind readnone
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define internal <8 x float> @__rcp_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; float iv = __rcp_v(v);
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; return iv * (2. - v * iv);
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%call = call <8 x float> @llvm.x86.avx.rcp.ps(<8 x float> %0)
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; do one N-R iteration
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%v_iv = fmul <8 x float> %0, %call
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%two_minus = fsub <8 x float> <float 2., float 2., float 2., float 2.,
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float 2., float 2., float 2., float 2.>, %v_iv
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%iv_mul = fmul <8 x float> %call, %two_minus
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ret <8 x float> %iv_mul
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}
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define internal float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; uniform float iv = extract(__rcp_u(v), 0);
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; return iv * (2. - v * iv);
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%vecval = insertelement <8 x float> undef, float %0, i32 0
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%call = call <8 x float> @llvm.x86.avx.rcp.ss(<8 x float> %vecval)
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%scall = extractelement <8 x float> %call, i32 0
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; do one N-R iteration
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%v_iv = fmul float %0, %scall
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%two_minus = fsub float 2., %v_iv
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%iv_mul = fmul float %scall, %two_minus
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ret float %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding
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declare <8 x float> @llvm.x86.avx.round.ps(<8 x float>, i32) nounwind readnone
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declare <8 x float> @llvm.x86.avx.round.ss(<8 x float>, <8 x float>, i32) nounwind readnone
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define internal <8 x float> @__round_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; roundps, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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%call = call <8 x float> @llvm.x86.avx.round.ps(<8 x float> %0, i32 8)
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ret <8 x float> %call
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}
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define internal float @__round_uniform_float(float) nounwind readonly alwaysinline {
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; roundss, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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; the roundss intrinsic is a total mess--docs say:
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;
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; __m128 _mm_round_ss (__m128 a, __m128 b, const int c)
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;
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; b is a 128-bit parameter. The lowest 32 bits are the result of the rounding function
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; on b0. The higher order 96 bits are copied directly from input parameter a. The
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; return value is described by the following equations:
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;
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; r0 = RND(b0)
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; r1 = a1
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; r2 = a2
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; r3 = a3
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;
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; It doesn't matter what we pass as a, since we only need the r0 value
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; here. So we pass the same register for both.
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%xi = insertelement <8 x float> undef, float %0, i32 0
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%xr = call <8 x float> @llvm.x86.avx.round.ss(<8 x float> %xi, <8 x float> %xi, i32 8)
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%rs = extractelement <8 x float> %xr, i32 0
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ret float %rs
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}
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define internal <8 x float> @__floor_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; roundps, round down 0b01 | don't signal precision exceptions 0b1000 = 9
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%call = call <8 x float> @llvm.x86.avx.round.ps(<8 x float> %0, i32 9)
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ret <8 x float> %call
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}
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define internal float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <8 x float> undef, float %0, i32 0
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; roundps, round down 0b01 | don't signal precision exceptions 0b1000 = 9
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%xr = call <8 x float> @llvm.x86.avx.round.ss(<8 x float> %xi, <8 x float> %xi, i32 9)
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%rs = extractelement <8 x float> %xr, i32 0
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ret float %rs
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}
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define internal <8 x float> @__ceil_varying_float(<8 x float>) nounwind readonly alwaysinline {
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; roundps, round up 0b10 | don't signal precision exceptions 0b1000 = 10
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%call = call <8 x float> @llvm.x86.avx.round.ps(<8 x float> %0, i32 10)
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ret <8 x float> %call
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}
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define internal float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <8 x float> undef, float %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1000 = 10
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%xr = call <8 x float> @llvm.x86.avx.round.ss(<8 x float> %xi, <8 x float> %xi, i32 10)
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%rs = extractelement <8 x float> %xr, i32 0
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ret float %rs
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}
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declare <8 x float> @llvm.x86.avx.rsqrt.ps(<8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.rsqrt.ss(<8 x float>) nounwind readnone
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define internal <8 x float> @__rsqrt_varying_float(<8 x float> %v) nounwind readonly alwaysinline {
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; float is = __rsqrt_v(v);
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%is = call <8 x float> @llvm.x86.avx.rsqrt.ps(<8 x float> %v)
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul <8 x float> %v, %is
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%v_is_is = fmul <8 x float> %v_is, %is
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%three_sub = fsub <8 x float> <float 3., float 3., float 3., float 3., float 3., float 3., float 3., float 3.>, %v_is_is
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%is_mul = fmul <8 x float> %is, %three_sub
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%half_scale = fmul <8 x float> <float 0.5, float 0.5, float 0.5, float 0.5, float 0.5, float 0.5, float 0.5, float 0.5>, %is_mul
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ret <8 x float> %half_scale
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}
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define internal float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
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; uniform float is = extract(__rsqrt_u(v), 0);
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%v = insertelement <8 x float> undef, float %0, i32 0
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%vis = call <8 x float> @llvm.x86.avx.rsqrt.ss(<8 x float> %v)
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%is = extractelement <8 x float> %vis, i32 0
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul float %0, %is
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%v_is_is = fmul float %v_is, %is
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%three_sub = fsub float 3., %v_is_is
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%is_mul = fmul float %is, %three_sub
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%half_scale = fmul float 0.5, %is_mul
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ret float %half_scale
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; sqrt
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declare <8 x float> @llvm.x86.avx.sqrt.ps(<8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.sqrt.ss(<8 x float>) nounwind readnone
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define internal <8 x float> @__sqrt_varying_float(<8 x float>) nounwind readonly alwaysinline {
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%call = call <8 x float> @llvm.x86.avx.sqrt.ps(<8 x float> %0)
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ret <8 x float> %call
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}
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define internal float @__sqrt_uniform_float(float) nounwind readonly alwaysinline {
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sse_unary_scalar(ret, 8, float, @llvm.x86.avx.sqrt.ss, %0)
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; fastmath
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declare void @llvm.x86.avx.stmxcsr(i32 *) nounwind
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declare void @llvm.x86.avx.ldmxcsr(i32 *) nounwind
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define internal void @__fastmath() nounwind alwaysinline {
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%ptr = alloca i32
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call void @llvm.x86.avx.stmxcsr(i32 * %ptr)
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%oldval = load i32 *%ptr
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; turn on DAZ (64)/FTZ (32768) -> 32832
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%update = or i32 %oldval, 32832
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store i32 %update, i32 *%ptr
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call void @llvm.x86.avx.ldmxcsr(i32 * %ptr)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; svml
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; FIXME: need either to wire these up to the 8-wide SVML entrypoints,
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; or, use the macro to call the 4-wide ones twice with our 8-wide
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; vectors...
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declare <8 x float> @__svml_sin(<8 x float>)
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declare <8 x float> @__svml_cos(<8 x float>)
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declare void @__svml_sincos(<8 x float>, <8 x float> *, <8 x float> *)
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declare <8 x float> @__svml_tan(<8 x float>)
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declare <8 x float> @__svml_atan(<8 x float>)
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declare <8 x float> @__svml_atan2(<8 x float>, <8 x float>)
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declare <8 x float> @__svml_exp(<8 x float>)
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declare <8 x float> @__svml_log(<8 x float>)
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declare <8 x float> @__svml_pow(<8 x float>, <8 x float>)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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declare <8 x float> @llvm.x86.avx.max.ps(<8 x float>, <8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.max.ss(<8 x float>, <8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.min.ps(<8 x float>, <8 x float>) nounwind readnone
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declare <8 x float> @llvm.x86.avx.min.ss(<8 x float>, <8 x float>) nounwind readnone
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define internal <8 x float> @__max_varying_float(<8 x float>,
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<8 x float>) nounwind readonly alwaysinline {
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%call = call <8 x float> @llvm.x86.avx.max.ps(<8 x float> %0, <8 x float> %1)
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ret <8 x float> %call
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}
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define internal float @__max_uniform_float(float, float) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 8, float, @llvm.x86.avx.max.ss, %0, %1)
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ret float %ret
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}
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define internal <8 x float> @__min_varying_float(<8 x float>,
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<8 x float>) nounwind readonly alwaysinline {
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%call = call <8 x float> @llvm.x86.avx.min.ps(<8 x float> %0, <8 x float> %1)
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ret <8 x float> %call
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}
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define internal float @__min_uniform_float(float, float) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 8, float, @llvm.x86.avx.min.ss, %0, %1)
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int min/max
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declare <8 x i32> @llvm.x86.avx.pminsd(<8 x i32>, <8 x i32>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx.pmaxsd(<8 x i32>, <8 x i32>) nounwind readnone
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define internal <8 x i32> @__min_varying_int32(<8 x i32>, <8 x i32>) nounwind readonly alwaysinline {
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%call = call <8 x i32> @llvm.x86.avx.pminsd(<8 x i32> %0, <8 x i32> %1)
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ret <8 x i32> %call
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}
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define internal i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 8, i32, @llvm.x86.avx.pminsd, %0, %1)
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ret i32 %ret
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}
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define internal <8 x i32> @__max_varying_int32(<8 x i32>, <8 x i32>) nounwind readonly alwaysinline {
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%call = call <8 x i32> @llvm.x86.avx.pmaxsd(<8 x i32> %0, <8 x i32> %1)
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ret <8 x i32> %call
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}
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define internal i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 8, i32, @llvm.x86.avx.pmaxsd, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unsigned int min/max
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declare <8 x i32> @llvm.x86.avx.pminud(<8 x i32>, <8 x i32>) nounwind readnone
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declare <8 x i32> @llvm.x86.avx.pmaxud(<8 x i32>, <8 x i32>) nounwind readnone
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define internal <8 x i32> @__min_varying_uint32(<8 x i32>,
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<8 x i32>) nounwind readonly alwaysinline {
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%call = call <8 x i32> @llvm.x86.avx.pminud(<8 x i32> %0, <8 x i32> %1)
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ret <8 x i32> %call
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}
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define internal i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 8, i32, @llvm.x86.avx.pminud, %0, %1)
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ret i32 %ret
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}
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define internal <8 x i32> @__max_varying_uint32(<8 x i32>,
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<8 x i32>) nounwind readonly alwaysinline {
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%call = call <8 x i32> @llvm.x86.avx.pmaxud(<8 x i32> %0, <8 x i32> %1)
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ret <8 x i32> %call
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}
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define internal i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 8, i32, @llvm.x86.avx.pmaxud, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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define internal i32 @__popcnt(i32) nounwind readonly alwaysinline {
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%call = call i32 @llvm.ctpop.i32(i32 %0)
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ret i32 %call
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}
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declare i32 @llvm.x86.avx.movmsk.ps(<8 x float>) nounwind readnone
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define internal i32 @__movmsk(<8 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <8 x i32> %0 to <8 x float>
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%v = call i32 @llvm.x86.avx.movmsk.ps(<8 x float> %floatmask) nounwind readnone
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ret i32 %v
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; horizontal float ops
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declare <8 x float> @llvm.x86.avx.hadd.ps(<8 x float>, <8 x float>) nounwind readnone
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define internal float @__reduce_add_float(<8 x float>) nounwind readonly alwaysinline {
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%v1 = call <8 x float> @llvm.x86.avx.hadd.ps(<8 x float> %0, <8 x float> %0)
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%v2 = call <8 x float> @llvm.x86.avx.hadd.ps(<8 x float> %v1, <8 x float> %v1)
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%scalar1 = extractelement <8 x float> %v2, i32 0
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%scalar2 = extractelement <8 x float> %v2, i32 4
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%sum = fadd float %scalar1, %scalar2
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ret float %sum
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}
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define internal float @__reduce_min_float(<8 x float>) nounwind readnone alwaysinline {
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reduce8(float, @__min_varying_float, @__min_uniform_float)
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}
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define internal float @__reduce_max_float(<8 x float>) nounwind readnone alwaysinline {
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reduce8(float, @__max_varying_float, @__max_uniform_float)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; horizontal int32 ops
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define internal <8 x i32> @__add_varying_int32(<8 x i32>,
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<8 x i32>) nounwind readnone alwaysinline {
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%s = add <8 x i32> %0, %1
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ret <8 x i32> %s
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}
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define internal i32 @__add_uniform_int32(i32, i32) nounwind readnone alwaysinline {
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%s = add i32 %0, %1
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ret i32 %s
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}
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define internal i32 @__reduce_add_int32(<8 x i32>) nounwind readnone alwaysinline {
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reduce8(i32, @__add_varying_int32, @__add_uniform_int32)
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}
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define internal i32 @__reduce_min_int32(<8 x i32>) nounwind readnone alwaysinline {
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reduce8(i32, @__min_varying_int32, @__min_uniform_int32)
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}
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define internal i32 @__reduce_max_int32(<8 x i32>) nounwind readnone alwaysinline {
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reduce8(i32, @__max_varying_int32, @__max_uniform_int32)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;; horizontal uint32 ops
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define internal i32 @__reduce_add_uint32(<8 x i32> %v) nounwind readnone alwaysinline {
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%r = call i32 @__reduce_add_int32(<8 x i32> %v)
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ret i32 %r
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}
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define internal i32 @__reduce_min_uint32(<8 x i32>) nounwind readnone alwaysinline {
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reduce8(i32, @__min_varying_uint32, @__min_uniform_uint32)
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}
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define internal i32 @__reduce_max_uint32(<8 x i32>) nounwind readnone alwaysinline {
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reduce8(i32, @__max_varying_uint32, @__max_uniform_uint32)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unaligned loads/loads+broadcasts
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define <8 x i32> @__load_and_broadcast_32(i8 *, <8 x i32> %mask) nounwind alwaysinline {
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%mm = call i32 @__movmsk(<8 x i32> %mask)
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%any_on = icmp ne i32 %mm, 0
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br i1 %any_on, label %load, label %skip
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load:
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%ptr = bitcast i8 * %0 to i32 *
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%val = load i32 * %ptr
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%ret0 = insertelement <8 x i32> undef, i32 %val, i32 0
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%ret1 = insertelement <8 x i32> %ret0, i32 %val, i32 1
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%ret2 = insertelement <8 x i32> %ret1, i32 %val, i32 2
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%ret3 = insertelement <8 x i32> %ret2, i32 %val, i32 3
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%ret4 = insertelement <8 x i32> %ret3, i32 %val, i32 4
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%ret5 = insertelement <8 x i32> %ret4, i32 %val, i32 5
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%ret6 = insertelement <8 x i32> %ret5, i32 %val, i32 6
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%ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7
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ret <8 x i32> %ret7
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skip:
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ret <8 x i32> undef
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}
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define <8 x i64> @__load_and_broadcast_64(i8 *, <8 x i32> %mask) nounwind alwaysinline {
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%mm = call i32 @__movmsk(<8 x i32> %mask)
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%any_on = icmp ne i32 %mm, 0
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br i1 %any_on, label %load, label %skip
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load:
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%ptr = bitcast i8 * %0 to i64 *
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%val = load i64 * %ptr
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%ret0 = insertelement <8 x i64> undef, i64 %val, i32 0
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%ret1 = insertelement <8 x i64> %ret0, i64 %val, i32 1
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%ret2 = insertelement <8 x i64> %ret1, i64 %val, i32 2
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%ret3 = insertelement <8 x i64> %ret2, i64 %val, i32 3
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%ret4 = insertelement <8 x i64> %ret3, i64 %val, i32 4
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%ret5 = insertelement <8 x i64> %ret4, i64 %val, i32 5
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%ret6 = insertelement <8 x i64> %ret5, i64 %val, i32 6
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%ret7 = insertelement <8 x i64> %ret6, i64 %val, i32 7
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ret <8 x i64> %ret3
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skip:
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ret <8 x i64> undef
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}
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define <8 x i32> @__load_masked_32(i8 *, <8 x i32> %mask) nounwind alwaysinline {
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%mm = call i32 @__movmsk(<8 x i32> %mask)
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%any_on = icmp ne i32 %mm, 0
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br i1 %any_on, label %load, label %skip
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load:
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%ptr = bitcast i8 * %0 to <8 x i32> *
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%val = load <8 x i32> * %ptr, align 4
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ret <8 x i32> %val
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skip:
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ret <8 x i32> undef
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}
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define <8 x i64> @__load_masked_64(i8 *, <8 x i32> %mask) nounwind alwaysinline {
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%mm = call i32 @__movmsk(<8 x i32> %mask)
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%any_on = icmp ne i32 %mm, 0
|
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br i1 %any_on, label %load, label %skip
|
|
|
|
load:
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|
%ptr = bitcast i8 * %0 to <8 x i64> *
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%val = load <8 x i64> * %ptr, align 8
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ret <8 x i64> %val
|
|
|
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skip:
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|
ret <8 x i64> undef
|
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
|
|
|
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define void @__masked_store_32(<8 x i32>* nocapture, <8 x i32>,
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<8 x i32>) nounwind alwaysinline {
|
|
per_lane(8, <8 x i32> %2, `
|
|
; compute address for this one
|
|
%ptr_ID = getelementptr <8 x i32> * %0, i32 0, i32 LANE
|
|
%storeval_ID = extractelement <8 x i32> %1, i32 LANE
|
|
store i32 %storeval_ID, i32 * %ptr_ID')
|
|
ret void
|
|
}
|
|
|
|
define void @__masked_store_64(<8 x i64>* nocapture, <8 x i64>,
|
|
<8 x i32>) nounwind alwaysinline {
|
|
per_lane(8, <8 x i32> %2, `
|
|
%ptr_ID = getelementptr <8 x i64> * %0, i32 0, i32 LANE
|
|
%storeval_ID = extractelement <8 x i64> %1, i32 LANE
|
|
store i64 %storeval_ID, i64 * %ptr_ID')
|
|
ret void
|
|
}
|
|
|
|
|
|
declare <8 x float> @llvm.x86.avx.blendvps(<8 x float>, <8 x float>,
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|
<8 x float>) nounwind readnone
|
|
|
|
|
|
define void @__masked_store_blend_32(<8 x i32>* nocapture, <8 x i32>,
|
|
<8 x i32>) nounwind alwaysinline {
|
|
%mask_as_float = bitcast <8 x i32> %2 to <8 x float>
|
|
%oldValue = load <8 x i32>* %0
|
|
%oldAsFloat = bitcast <8 x i32> %oldValue to <8 x float>
|
|
%newAsFloat = bitcast <8 x i32> %1 to <8 x float>
|
|
%blend = call <8 x float> @llvm.x86.avx.blendvps(<8 x float> %oldAsFloat,
|
|
<8 x float> %newAsFloat,
|
|
<8 x float> %mask_as_float)
|
|
%blendAsInt = bitcast <8 x float> %blend to <8 x i32>
|
|
store <8 x i32> %blendAsInt, <8 x i32>* %0
|
|
ret void
|
|
}
|
|
|
|
|
|
define void @__masked_store_blend_64(<8 x i64>* nocapture, <8 x i64>,
|
|
<8 x i32>) nounwind alwaysinline {
|
|
; always just serialize it
|
|
; FIXME: should implement the "do two 32-bit masked stores" stuff that
|
|
; other targets do...
|
|
call void @__masked_store_64(<8 x i64>* nocapture %0, <8 x i64> %1, <8 x i32> %2)
|
|
ret void
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; gather/scatter
|
|
|
|
gen_gather(8, i32)
|
|
gen_gather(8, i64)
|
|
gen_scatter(8, i32)
|
|
gen_scatter(8, i64)
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; double precision sqrt
|
|
|
|
declare <4 x double> @llvm.x86.avx.sqrt.pd(<4 x double>) nounwind readnone
|
|
declare <4 x double> @llvm.x86.avx.sqrt.sd(<4 x double>) nounwind readnone
|
|
|
|
define internal <8 x double> @__sqrt_varying_double(<8 x double>) nounwind alwaysinline {
|
|
unary4to8(ret, double, @llvm.x86.avx.sqrt.pd, %0)
|
|
ret <8 x double> %ret
|
|
}
|
|
|
|
define internal double @__sqrt_uniform_double(double) nounwind alwaysinline {
|
|
sse_unary_scalar(ret, 4, double, @llvm.x86.avx.sqrt.pd, %0)
|
|
ret double %ret
|
|
}
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; double precision min/max
|
|
|
|
declare <4 x double> @llvm.x86.avx.max.pd(<4 x double>, <4 x double>) nounwind readnone
|
|
declare <4 x double> @llvm.x86.avx.max.sd(<4 x double>, <4 x double>) nounwind readnone
|
|
declare <4 x double> @llvm.x86.avx.min.pd(<4 x double>, <4 x double>) nounwind readnone
|
|
declare <4 x double> @llvm.x86.avx.min.sd(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
define internal <8 x double> @__min_varying_double(<8 x double>, <8 x double>) nounwind readnone alwaysinline {
|
|
binary4to8(ret, double, @llvm.x86.avx.min.pd, %0, %1)
|
|
ret <8 x double> %ret
|
|
}
|
|
|
|
define internal double @__min_uniform_double(double, double) nounwind readnone alwaysinline {
|
|
sse_binary_scalar(ret, 4, double, @llvm.x86.avx.min.pd, %0, %1)
|
|
ret double %ret
|
|
}
|
|
|
|
define internal <8 x double> @__max_varying_double(<8 x double>, <8 x double>) nounwind readnone alwaysinline {
|
|
binary4to8(ret, double, @llvm.x86.avx.max.pd, %0, %1)
|
|
ret <8 x double> %ret
|
|
}
|
|
|
|
define internal double @__max_uniform_double(double, double) nounwind readnone alwaysinline {
|
|
sse_binary_scalar(ret, 4, double, @llvm.x86.avx.max.pd, %0, %1)
|
|
ret double %ret
|
|
}
|