301 lines
13 KiB
LLVM
301 lines
13 KiB
LLVM
;; Copyright (c) 2010-2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Define common 4-wide stuff
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stdlib_core(4)
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packed_load_and_store(4)
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scans(4)
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; Define the stuff that can be done with base SSE1/SSE2 instructions
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include(`builtins-sse.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
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declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
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define internal <4 x float> @__round_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 8)
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ret <4 x float> %call
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}
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define internal float @__round_uniform_float(float) nounwind readonly alwaysinline {
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; roundss, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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; the roundss intrinsic is a total mess--docs say:
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;
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; __m128 _mm_round_ss (__m128 a, __m128 b, const int c)
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;
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; b is a 128-bit parameter. The lowest 32 bits are the result of the rounding function
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; on b0. The higher order 96 bits are copied directly from input parameter a. The
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; return value is described by the following equations:
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;
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; r0 = RND(b0)
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; r1 = a1
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; r2 = a2
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; r3 = a3
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;
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; It doesn't matter what we pass as a, since we only need the r0 value
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; here. So we pass the same register for both. Further, only the 0th
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; element of the b parameter matters
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%xi = insertelement <4 x float> undef, float %0, i32 0
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 8)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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define internal <4 x float> @__floor_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round down 0b01 | don't signal precision exceptions 0b1000 = 9
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 9)
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ret <4 x float> %call
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}
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define internal float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round down 0b01 | don't signal precision exceptions 0b1000 = 9
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 9)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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define internal <4 x float> @__ceil_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round up 0b10 | don't signal precision exceptions 0b1000 = 10
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 10)
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ret <4 x float> %call
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}
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define internal float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1000 = 10
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 10)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
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declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
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define internal <4 x double> @__round_varying_double(<4 x double>) nounwind readonly alwaysinline {
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round2to4double(%0, 8)
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}
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define internal double @__round_uniform_double(double) nounwind readonly alwaysinline {
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%xi = insertelement <2 x double> undef, double %0, i32 0
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 8)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define internal <4 x double> @__floor_varying_double(<4 x double>) nounwind readonly alwaysinline {
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1000 = 9
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round2to4double(%0, 9)
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}
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define internal double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1000 = 9
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define internal <4 x double> @__ceil_varying_double(<4 x double>) nounwind readonly alwaysinline {
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; roundpd, round up 0b10 | don't signal precision exceptions 0b1000 = 10
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round2to4double(%0, 10)
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}
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define internal double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1000 = 10
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 min/max
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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define internal <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pminsd, %0, %1)
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ret i32 %ret
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}
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define internal <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pmaxsd, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; unsigned int min/max
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declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
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define internal <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pminud, %0, %1)
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ret i32 %ret
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}
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define internal <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pmaxud, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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define internal i32 @__popcnt_int32(i32) nounwind readonly alwaysinline {
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%call = call i32 @llvm.ctpop.i32(i32 %0)
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ret i32 %call
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}
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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define internal i64 @__popcnt_int64(i64) nounwind readonly alwaysinline {
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%call = call i64 @llvm.ctpop.i64(i64 %0)
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ret i64 %call
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}
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declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
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define internal float @__reduce_add_float(<4 x float>) nounwind readonly alwaysinline {
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%v1 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x float> %0)
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%v2 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %v1, <4 x float> %v1)
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%scalar = extractelement <4 x float> %v2, i32 0
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ret float %scalar
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
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declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>,
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<4 x float>) nounwind readnone
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define void @__masked_store_blend_32(<4 x i32>* nocapture, <4 x i32>,
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<4 x i32> %mask) nounwind alwaysinline {
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%mask_as_float = bitcast <4 x i32> %mask to <4 x float>
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%oldValue = load <4 x i32>* %0, align 4
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%oldAsFloat = bitcast <4 x i32> %oldValue to <4 x float>
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%newAsFloat = bitcast <4 x i32> %1 to <4 x float>
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%blend = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %oldAsFloat,
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<4 x float> %newAsFloat,
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<4 x float> %mask_as_float)
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%blendAsInt = bitcast <4 x float> %blend to <4 x i32>
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store <4 x i32> %blendAsInt, <4 x i32>* %0, align 4
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ret void
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}
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define void @__masked_store_blend_64(<4 x i64>* nocapture %ptr, <4 x i64> %new,
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<4 x i32> %i32mask) nounwind alwaysinline {
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%oldValue = load <4 x i64>* %ptr, align 8
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%mask = bitcast <4 x i32> %i32mask to <4 x float>
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; Do 4x64-bit blends by doing two <4 x i32> blends, where the <4 x i32> values
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; are actually bitcast <2 x i64> values
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;
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; set up the first two 64-bit values
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%old01 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%old01f = bitcast <2 x i64> %old01 to <4 x float>
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%new01 = shufflevector <4 x i64> %new, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%new01f = bitcast <2 x i64> %new01 to <4 x float>
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; compute mask--note that the indices 0 and 1 are doubled-up
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%mask01 = shufflevector <4 x float> %mask, <4 x float> undef,
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<4 x i32> <i32 0, i32 0, i32 1, i32 1>
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; and blend the two of the values
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%result01f = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %old01f,
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<4 x float> %new01f,
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<4 x float> %mask01)
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%result01 = bitcast <4 x float> %result01f to <2 x i64>
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; and again
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%old23 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%old23f = bitcast <2 x i64> %old23 to <4 x float>
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%new23 = shufflevector <4 x i64> %new, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%new23f = bitcast <2 x i64> %new23 to <4 x float>
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; compute mask--note that the values 2 and 3 are doubled-up
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%mask23 = shufflevector <4 x float> %mask, <4 x float> undef,
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<4 x i32> <i32 2, i32 2, i32 3, i32 3>
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; and blend the two of the values
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%result23f = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %old23f,
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<4 x float> %new23f,
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<4 x float> %mask23)
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%result23 = bitcast <4 x float> %result23f to <2 x i64>
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; reconstruct the final <4 x i64> vector
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%final = shufflevector <2 x i64> %result01, <2 x i64> %result23,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i64> %final, <4 x i64> * %ptr, align 8
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ret void
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}
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