ab3b633733
Like SSE4-8 and SSE4-16, these use 8-bit and 16-bit values for mask elements, respectively, and thus should generate the best code when used for computation with datatypes of those sizes.
459 lines
17 KiB
LLVM
459 lines
17 KiB
LLVM
;;
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;; target-neon-16.ll
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;;
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;; Copyright(c) 2013 Google, Inc.
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;;
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Matt Pharr nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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define(`WIDTH',`8')
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define(`MASK',`i16')
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include(`util.m4')
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include(`target-neon-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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define <8 x float> @__half_to_float_varying(<8 x i16> %v) nounwind readnone {
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unary4to8conv(r, i16, float, @llvm.arm.neon.vcvthf2fp, %v)
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ret <8 x float> %r
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}
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define <8 x i16> @__float_to_half_varying(<8 x float> %v) nounwind readnone {
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unary4to8conv(r, float, i16, @llvm.arm.neon.vcvtfp2hf, %v)
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ret <8 x i16> %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; math
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;; round/floor/ceil
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;; FIXME: grabbed these from the sse2 target, which does not have native
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;; instructions for these. Is there a better approach for NEON?
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define <8 x float> @__round_varying_float(<8 x float>) nounwind readonly alwaysinline {
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%float_to_int_bitcast.i.i.i.i = bitcast <8 x float> %0 to <8 x i32>
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%bitop.i.i = and <8 x i32> %float_to_int_bitcast.i.i.i.i,
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<i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648,
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i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%bitop.i = xor <8 x i32> %float_to_int_bitcast.i.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i40.i = bitcast <8 x i32> %bitop.i to <8 x float>
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%binop.i = fadd <8 x float> %int_to_float_bitcast.i.i40.i,
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<float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06,
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float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>
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%binop21.i = fadd <8 x float> %binop.i,
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<float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06,
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float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06>
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%float_to_int_bitcast.i.i.i = bitcast <8 x float> %binop21.i to <8 x i32>
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%bitop31.i = xor <8 x i32> %float_to_int_bitcast.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i.i = bitcast <8 x i32> %bitop31.i to <8 x float>
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ret <8 x float> %int_to_float_bitcast.i.i.i
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}
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define <8 x float> @__floor_varying_float(<8 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <8 x float> @__round_varying_float(<8 x float> %0) nounwind
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%bincmp.i = fcmp ogt <8 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <8 x i1> %bincmp.i to <8 x i32>
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%bitop.i = and <8 x i32> %val_to_boolvec32.i,
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<i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432,
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i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432>
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%int_to_float_bitcast.i.i.i = bitcast <8 x i32> %bitop.i to <8 x float>
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%binop.i = fadd <8 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <8 x float> %binop.i
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}
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define <8 x float> @__ceil_varying_float(<8 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <8 x float> @__round_varying_float(<8 x float> %0) nounwind
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%bincmp.i = fcmp olt <8 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <8 x i1> %bincmp.i to <8 x i32>
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%bitop.i = and <8 x i32> %val_to_boolvec32.i,
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<i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216,
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i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
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%int_to_float_bitcast.i.i.i = bitcast <8 x i32> %bitop.i to <8 x float>
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%binop.i = fadd <8 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <8 x float> %binop.i
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}
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;; FIXME: rounding doubles and double vectors needs to be implemented
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declare <WIDTH x double> @__round_varying_double(<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__floor_varying_double(<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__ceil_varying_double(<WIDTH x double>) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; min/max
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declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__max_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone {
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binary4to8(r, float, @llvm.arm.neon.vmaxs.v4f32, %0, %1)
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ret <WIDTH x float> %r
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}
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define <WIDTH x float> @__min_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone {
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binary4to8(r, float, @llvm.arm.neon.vmins.v4f32, %0, %1)
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ret <WIDTH x float> %r
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}
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declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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define <WIDTH x i32> @__min_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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binary4to8(r, i32, @llvm.arm.neon.vmins.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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define <WIDTH x i32> @__max_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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binary4to8(r, i32, @llvm.arm.neon.vmaxs.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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define <WIDTH x i32> @__min_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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binary4to8(r, i32, @llvm.arm.neon.vminu.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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define <WIDTH x i32> @__max_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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binary4to8(r, i32, @llvm.arm.neon.vmaxu.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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;; sqrt/rsqrt/rcp
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__rcp_varying_float(<WIDTH x float> %d) nounwind readnone {
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unary4to8(x0, float, @llvm.arm.neon.vrecpe.v4f32, %d)
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binary4to8(x0_nr, float, @llvm.arm.neon.vrecps.v4f32, %d, %x0)
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%x1 = fmul <WIDTH x float> %x0, %x0_nr
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binary4to8(x1_nr, float, @llvm.arm.neon.vrecps.v4f32, %d, %x1)
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%x2 = fmul <WIDTH x float> %x1, %x1_nr
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ret <WIDTH x float> %x2
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}
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declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %d) nounwind readnone {
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unary4to8(x0, float, @llvm.arm.neon.vrsqrte.v4f32, %d)
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%x0_2 = fmul <WIDTH x float> %x0, %x0
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binary4to8(x0_nr, float, @llvm.arm.neon.vrsqrts.v4f32, %d, %x0_2)
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%x1 = fmul <WIDTH x float> %x0, %x0_nr
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%x1_2 = fmul <WIDTH x float> %x1, %x1
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binary4to8(x1_nr, float, @llvm.arm.neon.vrsqrts.v4f32, %d, %x1_2)
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%x2 = fmul <WIDTH x float> %x1, %x1_nr
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ret <WIDTH x float> %x2
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}
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define float @__rsqrt_uniform_float(float) nounwind readnone {
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%v1 = bitcast float %0 to <1 x float>
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%vs = shufflevector <1 x float> %v1, <1 x float> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%vr = call <8 x float> @__rsqrt_varying_float(<8 x float> %vs)
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%r = extractelement <8 x float> %vr, i32 0
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ret float %r
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}
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define float @__rcp_uniform_float(float) nounwind readnone {
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%v1 = bitcast float %0 to <1 x float>
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%vs = shufflevector <1 x float> %v1, <1 x float> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%vr = call <8 x float> @__rcp_varying_float(<8 x float> %vs)
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%r = extractelement <8 x float> %vr, i32 0
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ret float %r
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}
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
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define <WIDTH x float> @__sqrt_varying_float(<WIDTH x float>) nounwind readnone {
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unary4to8(result, float, @llvm.sqrt.v4f32, %0)
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;; this returns nan for v=0, which is undesirable..
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;; %rsqrt = call <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %0)
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;; %result = fmul <4 x float> %rsqrt, %0
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ret <8 x float> %result
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}
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declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
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define <WIDTH x double> @__sqrt_varying_double(<WIDTH x double>) nounwind readnone {
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unary4to8(r, double, @llvm.sqrt.v4f64, %0)
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ret <WIDTH x double> %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; reductions
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define i64 @__movmsk(<WIDTH x MASK>) nounwind readnone {
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%and_mask = and <WIDTH x i16> %0,
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<i16 1, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128>
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%v4 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %and_mask)
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%v2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %v4)
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%va = extractelement <2 x i64> %v2, i32 0
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%vb = extractelement <2 x i64> %v2, i32 1
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%v = or i64 %va, %vb
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ret i64 %v
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}
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define i1 @__any(<WIDTH x MASK>) nounwind readnone alwaysinline {
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v8tov4(MASK, %0, %v0123, %v4567)
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%vor = or <4 x MASK> %v0123, %v4567
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%v0 = extractelement <4 x MASK> %vor, i32 0
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%v1 = extractelement <4 x MASK> %vor, i32 1
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%v2 = extractelement <4 x MASK> %vor, i32 2
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%v3 = extractelement <4 x MASK> %vor, i32 3
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%v01 = or MASK %v0, %v1
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%v23 = or MASK %v2, %v3
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%v = or MASK %v01, %v23
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%cmp = icmp ne MASK %v, 0
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ret i1 %cmp
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}
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define i1 @__all(<WIDTH x MASK>) nounwind readnone alwaysinline {
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v8tov4(MASK, %0, %v0123, %v4567)
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%vand = and <4 x MASK> %v0123, %v4567
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%v0 = extractelement <4 x MASK> %vand, i32 0
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%v1 = extractelement <4 x MASK> %vand, i32 1
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%v2 = extractelement <4 x MASK> %vand, i32 2
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%v3 = extractelement <4 x MASK> %vand, i32 3
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%v01 = and MASK %v0, %v1
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%v23 = and MASK %v2, %v3
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%v = and MASK %v01, %v23
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%cmp = icmp ne MASK %v, 0
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ret i1 %cmp
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}
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define i1 @__none(<WIDTH x MASK>) nounwind readnone alwaysinline {
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%any = call i1 @__any(<WIDTH x MASK> %0)
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%none = icmp eq i1 %any, 0
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ret i1 %none
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}
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;; $1: scalar type
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;; $2: vector/vector reduce function (2 x <WIDTH x vec> -> <WIDTH x vec>)
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;; $3: pairwise vector reduce function (2 x <2 x vec> -> <2 x vec>)
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;; $4: scalar reduce function
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define(`neon_reduce', `
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v8tov4($1, %0, %v0123, %v4567)
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%v0123_8 = shufflevector <4 x $1> %v0123, <4 x $1> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%v4567_8 = shufflevector <4 x $1> %v4567, <4 x $1> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%vfirst = call <8 x $1> $2(<8 x $1> %v0123_8, <8 x $1> %v4567_8)
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%vfirst_4 = shufflevector <8 x $1> %vfirst, <8 x $1> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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v4tov2($1, %vfirst_4, %v0, %v1)
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%vh = call <2 x $1> $3(<2 x $1> %v0, <2 x $1> %v1)
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%vh0 = extractelement <2 x $1> %vh, i32 0
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%vh1 = extractelement <2 x $1> %vh, i32 1
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%r = call $1 $4($1 %vh0, $1 %vh1)
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ret $1 %r
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')
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declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define internal float @add_f32(float, float) {
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%r = fadd float %0, %1
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ret float %r
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}
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define internal <WIDTH x float> @__add_varying_float(<WIDTH x float>, <WIDTH x float>) {
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%r = fadd <WIDTH x float> %0, %1
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ret <WIDTH x float> %r
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}
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define float @__reduce_add_float(<WIDTH x float>) nounwind readnone {
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neon_reduce(float, @__add_varying_float, @llvm.arm.neon.vpadd.v2f32, @add_f32)
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}
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declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define internal float @min_f32(float, float) {
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%cmp = fcmp olt float %0, %1
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%r = select i1 %cmp, float %0, float %1
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ret float %r
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}
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define float @__reduce_min_float(<WIDTH x float>) nounwind readnone {
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neon_reduce(float, @__min_varying_float, @llvm.arm.neon.vpmins.v2f32, @min_f32)
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}
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declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define internal float @max_f32(float, float) {
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%cmp = fcmp ugt float %0, %1
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%r = select i1 %cmp, float %0, float %1
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ret float %r
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}
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define float @__reduce_max_float(<WIDTH x float>) nounwind readnone {
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neon_reduce(float, @__max_varying_float, @llvm.arm.neon.vpmaxs.v2f32, @max_f32)
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}
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declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
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define i16 @__reduce_add_int8(<WIDTH x i8>) nounwind readnone {
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%a16 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %0)
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%a32 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %a16)
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%a0 = extractelement <2 x i32> %a32, i32 0
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%a1 = extractelement <2 x i32> %a32, i32 1
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%r = add i32 %a0, %a1
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%r16 = trunc i32 %r to i16
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ret i16 %r16
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}
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declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<WIDTH x i16>)
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define i64 @__reduce_add_int16(<WIDTH x i16>) nounwind readnone {
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%a1 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<WIDTH x i16> %0)
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%a2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %a1)
|
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%aa = extractelement <2 x i64> %a2, i32 0
|
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%ab = extractelement <2 x i64> %a2, i32 1
|
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%r = add i64 %aa, %ab
|
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ret i64 %r
|
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}
|
|
|
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declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
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|
|
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define i64 @__reduce_add_int32(<WIDTH x i32>) nounwind readnone {
|
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v8tov4(i32, %0, %va, %vb)
|
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%pa = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %va)
|
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%pb = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %vb)
|
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%psum = add <2 x i64> %pa, %pb
|
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%a0 = extractelement <2 x i64> %psum, i32 0
|
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%a1 = extractelement <2 x i64> %psum, i32 1
|
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%r = add i64 %a0, %a1
|
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ret i64 %r
|
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}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
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define internal i32 @min_si32(i32, i32) {
|
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%cmp = icmp slt i32 %0, %1
|
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%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_min_int32(<WIDTH x i32>) nounwind readnone {
|
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neon_reduce(i32, @__min_varying_int32, @llvm.arm.neon.vpmins.v2i32, @min_si32)
|
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}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @max_si32(i32, i32) {
|
|
%cmp = icmp sgt i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_max_int32(<WIDTH x i32>) nounwind readnone {
|
|
neon_reduce(i32, @__max_varying_int32, @llvm.arm.neon.vpmaxs.v2i32, @max_si32)
|
|
}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @min_ui32(i32, i32) {
|
|
%cmp = icmp ult i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_min_uint32(<WIDTH x i32>) nounwind readnone {
|
|
neon_reduce(i32, @__min_varying_uint32, @llvm.arm.neon.vpmins.v2i32, @min_ui32)
|
|
}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @max_ui32(i32, i32) {
|
|
%cmp = icmp ugt i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_max_uint32(<WIDTH x i32>) nounwind readnone {
|
|
neon_reduce(i32, @__max_varying_uint32, @llvm.arm.neon.vpmaxs.v2i32, @max_ui32)
|
|
}
|
|
|
|
define double @__reduce_add_double(<WIDTH x double>) nounwind readnone {
|
|
v8tov2(double, %0, %v0, %v1, %v2, %v3)
|
|
%v01 = fadd <2 x double> %v0, %v1
|
|
%v23 = fadd <2 x double> %v2, %v3
|
|
%sum = fadd <2 x double> %v01, %v23
|
|
%e0 = extractelement <2 x double> %sum, i32 0
|
|
%e1 = extractelement <2 x double> %sum, i32 1
|
|
%m = fadd double %e0, %e1
|
|
ret double %m
|
|
}
|
|
|
|
define double @__reduce_min_double(<WIDTH x double>) nounwind readnone {
|
|
reduce8(double, @__min_varying_double, @__min_uniform_double)
|
|
}
|
|
|
|
define double @__reduce_max_double(<WIDTH x double>) nounwind readnone {
|
|
reduce8(double, @__max_varying_double, @__max_uniform_double)
|
|
}
|
|
|
|
define i64 @__reduce_add_int64(<WIDTH x i64>) nounwind readnone {
|
|
v8tov2(i64, %0, %v0, %v1, %v2, %v3)
|
|
%v01 = add <2 x i64> %v0, %v1
|
|
%v23 = add <2 x i64> %v2, %v3
|
|
%sum = add <2 x i64> %v01, %v23
|
|
%e0 = extractelement <2 x i64> %sum, i32 0
|
|
%e1 = extractelement <2 x i64> %sum, i32 1
|
|
%m = add i64 %e0, %e1
|
|
ret i64 %m
|
|
}
|
|
|
|
define i64 @__reduce_min_int64(<WIDTH x i64>) nounwind readnone {
|
|
reduce8(i64, @__min_varying_int64, @__min_uniform_int64)
|
|
}
|
|
|
|
define i64 @__reduce_max_int64(<WIDTH x i64>) nounwind readnone {
|
|
reduce8(i64, @__max_varying_int64, @__max_uniform_int64)
|
|
}
|
|
|
|
define i64 @__reduce_min_uint64(<WIDTH x i64>) nounwind readnone {
|
|
reduce8(i64, @__min_varying_uint64, @__min_uniform_uint64)
|
|
}
|
|
|
|
define i64 @__reduce_max_uint64(<WIDTH x i64>) nounwind readnone {
|
|
reduce8(i64, @__max_varying_uint64, @__max_uniform_uint64)
|
|
}
|