485 lines
18 KiB
LLVM
485 lines
18 KiB
LLVM
;; Copyright (c) 2010-2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Define common 4-wide stuff
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define(`WIDTH',`4')
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define(`MASK',`i32')
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include(`util.m4')
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stdlib_core()
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packed_load_and_store()
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scans()
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int64minmax()
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include(`target-sse4-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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declare float @__half_to_float_uniform(i16 %v) nounwind readnone
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declare <WIDTH x float> @__half_to_float_varying(<WIDTH x i16> %v) nounwind readnone
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declare i16 @__float_to_half_uniform(float %v) nounwind readnone
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declare <WIDTH x i16> @__float_to_half_varying(<WIDTH x float> %v) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
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define <4 x float> @__rcp_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %0)
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; do one N-R iteration to improve precision
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; float iv = __rcp_v(v);
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; return iv * (2. - v * iv);
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%v_iv = fmul <4 x float> %0, %call
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%two_minus = fsub <4 x float> <float 2., float 2., float 2., float 2.>, %v_iv
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%iv_mul = fmul <4 x float> %call, %two_minus
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ret <4 x float> %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; rsqrt
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declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
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define <4 x float> @__rsqrt_varying_float(<4 x float> %v) nounwind readonly alwaysinline {
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; float is = __rsqrt_v(v);
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%is = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %v)
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul <4 x float> %v, %is
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%v_is_is = fmul <4 x float> %v_is, %is
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%three_sub = fsub <4 x float> <float 3., float 3., float 3., float 3.>, %v_is_is
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%is_mul = fmul <4 x float> %is, %three_sub
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%half_scale = fmul <4 x float> <float 0.5, float 0.5, float 0.5, float 0.5>, %is_mul
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ret <4 x float> %half_scale
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; sqrt
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declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
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define <4 x float> @__sqrt_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %0)
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ret <4 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
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define <4 x double> @__sqrt_varying_double(<4 x double>) nounwind alwaysinline {
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unary2to4(ret, double, @llvm.x86.sse2.sqrt.pd, %0)
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ret <4 x double> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
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define <4 x float> @__round_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 8)
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ret <4 x float> %call
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}
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define <4 x float> @__floor_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 9)
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ret <4 x float> %call
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}
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define <4 x float> @__ceil_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 10)
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ret <4 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
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define <4 x double> @__round_varying_double(<4 x double>) nounwind readonly alwaysinline {
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round2to4double(%0, 8)
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}
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define <4 x double> @__floor_varying_double(<4 x double>) nounwind readonly alwaysinline {
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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round2to4double(%0, 9)
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}
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define <4 x double> @__ceil_varying_double(<4 x double>) nounwind readonly alwaysinline {
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; roundpd, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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round2to4double(%0, 10)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @__max_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %call
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}
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define <4 x float> @__min_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 min/max
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define <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; unsigned int min/max
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define <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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define <4 x double> @__min_varying_double(<4 x double>, <4 x double>) nounwind readnone {
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binary2to4(ret, double, @llvm.x86.sse2.min.pd, %0, %1)
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ret <4 x double> %ret
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}
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define <4 x double> @__max_varying_double(<4 x double>, <4 x double>) nounwind readnone {
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binary2to4(ret, double, @llvm.x86.sse2.max.pd, %0, %1)
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ret <4 x double> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; svml stuff
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declare <4 x float> @__svml_sinf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_cosf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_sincosf4(<4 x float> *, <4 x float>) nounwind readnone
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declare <4 x float> @__svml_tanf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_atanf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_atan2f4(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @__svml_expf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_logf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_powf4(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @__svml_sin(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_sinf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define <4 x float> @__svml_cos(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_cosf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define void @__svml_sincos(<4 x float>, <4 x float> *, <4 x float> *) nounwind readnone alwaysinline {
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%s = call <4 x float> @__svml_sincosf4(<4 x float> * %2, <4 x float> %0)
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store <4 x float> %s, <4 x float> * %1
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ret void
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}
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define <4 x float> @__svml_tan(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_tanf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define <4 x float> @__svml_atan(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_atanf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define <4 x float> @__svml_atan2(<4 x float>, <4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_atan2f4(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %ret
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}
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define <4 x float> @__svml_exp(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_expf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define <4 x float> @__svml_log(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_logf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define <4 x float> @__svml_pow(<4 x float>, <4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_powf4(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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define i32 @__movmsk(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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ret i32 %v
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}
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declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
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define float @__reduce_add_float(<4 x float>) nounwind readonly alwaysinline {
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%v1 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %0, <4 x float> %0)
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%v2 = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %v1, <4 x float> %v1)
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%scalar = extractelement <4 x float> %v2, i32 0
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ret float %scalar
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}
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define float @__reduce_min_float(<4 x float>) nounwind readnone {
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reduce4(float, @__min_varying_float, @__min_uniform_float)
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}
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define float @__reduce_max_float(<4 x float>) nounwind readnone {
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reduce4(float, @__max_varying_float, @__max_uniform_float)
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}
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define i32 @__reduce_add_int32(<4 x i32> %v) nounwind readnone {
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%v1 = shufflevector <4 x i32> %v, <4 x i32> undef,
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<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%m1 = add <4 x i32> %v1, %v
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%m1a = extractelement <4 x i32> %m1, i32 0
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%m1b = extractelement <4 x i32> %m1, i32 1
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%sum = add i32 %m1a, %m1b
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ret i32 %sum
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}
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define i32 @__reduce_min_int32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__min_varying_int32, @__min_uniform_int32)
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}
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define i32 @__reduce_max_int32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__max_varying_int32, @__max_uniform_int32)
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}
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define i32 @__reduce_add_uint32(<4 x i32> %v) nounwind readnone {
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%r = call i32 @__reduce_add_int32(<4 x i32> %v)
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ret i32 %r
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}
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define i32 @__reduce_min_uint32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__min_varying_uint32, @__min_uniform_uint32)
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}
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define i32 @__reduce_max_uint32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__max_varying_uint32, @__max_uniform_uint32)
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}
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define double @__reduce_add_double(<4 x double>) nounwind readnone {
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%v0 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 2, i32 3>
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%sum = fadd <2 x double> %v0, %v1
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%e0 = extractelement <2 x double> %sum, i32 0
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%e1 = extractelement <2 x double> %sum, i32 1
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%m = fadd double %e0, %e1
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ret double %m
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}
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define double @__reduce_min_double(<4 x double>) nounwind readnone {
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reduce4(double, @__min_varying_double, @__min_uniform_double)
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}
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define double @__reduce_max_double(<4 x double>) nounwind readnone {
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reduce4(double, @__max_varying_double, @__max_uniform_double)
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}
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define i64 @__reduce_add_int64(<4 x i64>) nounwind readnone {
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%v0 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%sum = add <2 x i64> %v0, %v1
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%e0 = extractelement <2 x i64> %sum, i32 0
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%e1 = extractelement <2 x i64> %sum, i32 1
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%m = add i64 %e0, %e1
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ret i64 %m
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}
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define i64 @__reduce_min_int64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__min_varying_int64, @__min_uniform_int64)
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}
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define i64 @__reduce_max_int64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__max_varying_int64, @__max_uniform_int64)
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}
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define i64 @__reduce_min_uint64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__min_varying_uint64, @__min_uniform_uint64)
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}
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define i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__max_varying_uint64, @__max_uniform_uint64)
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}
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reduce_equal(4)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
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declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>,
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<4 x float>) nounwind readnone
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define void @__masked_store_blend_32(<4 x i32>* nocapture, <4 x i32>,
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<4 x i32> %mask) nounwind alwaysinline {
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%mask_as_float = bitcast <4 x i32> %mask to <4 x float>
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%oldValue = load <4 x i32>* %0, align 4
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%oldAsFloat = bitcast <4 x i32> %oldValue to <4 x float>
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%newAsFloat = bitcast <4 x i32> %1 to <4 x float>
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%blend = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %oldAsFloat,
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<4 x float> %newAsFloat,
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<4 x float> %mask_as_float)
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%blendAsInt = bitcast <4 x float> %blend to <4 x i32>
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store <4 x i32> %blendAsInt, <4 x i32>* %0, align 4
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ret void
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}
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define void @__masked_store_blend_64(<4 x i64>* nocapture %ptr, <4 x i64> %new,
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<4 x i32> %i32mask) nounwind alwaysinline {
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%oldValue = load <4 x i64>* %ptr, align 8
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%mask = bitcast <4 x i32> %i32mask to <4 x float>
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; Do 4x64-bit blends by doing two <4 x i32> blends, where the <4 x i32> values
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; are actually bitcast <2 x i64> values
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;
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; set up the first two 64-bit values
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%old01 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%old01f = bitcast <2 x i64> %old01 to <4 x float>
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%new01 = shufflevector <4 x i64> %new, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%new01f = bitcast <2 x i64> %new01 to <4 x float>
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; compute mask--note that the indices 0 and 1 are doubled-up
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%mask01 = shufflevector <4 x float> %mask, <4 x float> undef,
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<4 x i32> <i32 0, i32 0, i32 1, i32 1>
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; and blend the two of the values
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%result01f = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %old01f,
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<4 x float> %new01f,
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<4 x float> %mask01)
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%result01 = bitcast <4 x float> %result01f to <2 x i64>
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; and again
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%old23 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%old23f = bitcast <2 x i64> %old23 to <4 x float>
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%new23 = shufflevector <4 x i64> %new, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%new23f = bitcast <2 x i64> %new23 to <4 x float>
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; compute mask--note that the values 2 and 3 are doubled-up
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%mask23 = shufflevector <4 x float> %mask, <4 x float> undef,
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<4 x i32> <i32 2, i32 2, i32 3, i32 3>
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; and blend the two of the values
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%result23f = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %old23f,
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<4 x float> %new23f,
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<4 x float> %mask23)
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%result23 = bitcast <4 x float> %result23f to <2 x i64>
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; reconstruct the final <4 x i64> vector
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%final = shufflevector <2 x i64> %result01, <2 x i64> %result23,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i64> %final, <4 x i64> * %ptr, align 8
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
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masked_store_blend_8_16_by_4()
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gen_masked_store(4, i8, 8)
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gen_masked_store(4, i16, 16)
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gen_masked_store(4, i32, 32)
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gen_masked_store(4, i64, 64)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unaligned loads/loads+broadcasts
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load_and_broadcast(4, i8, 8)
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load_and_broadcast(4, i16, 16)
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load_and_broadcast(4, i32, 32)
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|
load_and_broadcast(4, i64, 64)
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|
|
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masked_load(4, i8, 8, 1)
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|
masked_load(4, i16, 16, 2)
|
|
masked_load(4, i32, 32, 4)
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|
masked_load(4, i64, 64, 8)
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|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; gather/scatter
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|
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|
; define these with the macros from stdlib.m4
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|
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|
gen_gather(4, i8)
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|
gen_gather(4, i16)
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|
gen_gather(4, i32)
|
|
gen_gather(4, i64)
|
|
|
|
gen_scatter(4, i8)
|
|
gen_scatter(4, i16)
|
|
gen_scatter(4, i32)
|
|
gen_scatter(4, i64)
|