600 lines
22 KiB
LLVM
600 lines
22 KiB
LLVM
;; Copyright (c) 2010-2015, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Define the standard library builtins for the SSE2 target
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; Define some basics for a 4-wide target
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define(`WIDTH',`4')
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define(`MASK',`i32')
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include(`util.m4')
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stdlib_core()
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packed_load_and_store()
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scans()
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int64minmax()
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saturation_arithmetic()
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include(`target-sse2-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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declare float @__half_to_float_uniform(i16 %v) nounwind readnone
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declare <WIDTH x float> @__half_to_float_varying(<WIDTH x i16> %v) nounwind readnone
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declare i16 @__float_to_half_uniform(float %v) nounwind readnone
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declare <WIDTH x i16> @__float_to_half_varying(<WIDTH x float> %v) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding
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;;
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;; There are not any rounding instructions in SSE2, so we have to emulate
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;; the functionality with multiple instructions...
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; The code for __round_* is the result of compiling the following source
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; code.
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;
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; export float Round(float x) {
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; unsigned int sign = signbits(x);
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; unsigned int ix = intbits(x);
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; ix ^= sign;
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; x = floatbits(ix);
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; x += 0x1.0p23f;
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; x -= 0x1.0p23f;
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; ix = intbits(x);
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; ix ^= sign;
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; x = floatbits(ix);
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; return x;
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;}
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define <4 x float> @__round_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%float_to_int_bitcast.i.i.i.i = bitcast <4 x float> %0 to <4 x i32>
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%bitop.i.i = and <4 x i32> %float_to_int_bitcast.i.i.i.i, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%bitop.i = xor <4 x i32> %float_to_int_bitcast.i.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i40.i = bitcast <4 x i32> %bitop.i to <4 x float>
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%binop.i = fadd <4 x float> %int_to_float_bitcast.i.i40.i, <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>
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%binop21.i = fadd <4 x float> %binop.i, <float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06>
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%float_to_int_bitcast.i.i.i = bitcast <4 x float> %binop21.i to <4 x i32>
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%bitop31.i = xor <4 x i32> %float_to_int_bitcast.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i.i = bitcast <4 x i32> %bitop31.i to <4 x float>
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ret <4 x float> %int_to_float_bitcast.i.i.i
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}
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;; Similarly, for implementations of the __floor* functions below, we have the
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;; bitcode from compiling the following source code...
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;export float Floor(float x) {
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; float y = Round(x);
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; unsigned int cmp = y > x ? 0xffffffff : 0;
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; float delta = -1.f;
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; unsigned int idelta = intbits(delta);
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; idelta &= cmp;
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; delta = floatbits(idelta);
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; return y + delta;
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;}
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define <4 x float> @__floor_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <4 x float> @__round_varying_float(<4 x float> %0) nounwind
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%bincmp.i = fcmp ogt <4 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <4 x i1> %bincmp.i to <4 x i32>
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%bitop.i = and <4 x i32> %val_to_boolvec32.i, <i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432>
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%int_to_float_bitcast.i.i.i = bitcast <4 x i32> %bitop.i to <4 x float>
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%binop.i = fadd <4 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <4 x float> %binop.i
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}
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;; And here is the code we compiled to get the __ceil* functions below
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;
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;export uniform float Ceil(uniform float x) {
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; uniform float y = Round(x);
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; uniform int yltx = y < x ? 0xffffffff : 0;
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; uniform float delta = 1.f;
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; uniform int idelta = intbits(delta);
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; idelta &= yltx;
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; delta = floatbits(idelta);
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; return y + delta;
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;}
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define <4 x float> @__ceil_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <4 x float> @__round_varying_float(<4 x float> %0) nounwind
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%bincmp.i = fcmp olt <4 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <4 x i1> %bincmp.i to <4 x i32>
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%bitop.i = and <4 x i32> %val_to_boolvec32.i, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
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%int_to_float_bitcast.i.i.i = bitcast <4 x i32> %bitop.i to <4 x float>
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%binop.i = fadd <4 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <4 x float> %binop.i
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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define <4 x double> @__round_varying_double(<4 x double>) nounwind readonly alwaysinline {
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unary1to4(double, @round)
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}
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define <4 x double> @__floor_varying_double(<4 x double>) nounwind readonly alwaysinline {
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unary1to4(double, @floor)
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}
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define <4 x double> @__ceil_varying_double(<4 x double>) nounwind readonly alwaysinline {
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unary1to4(double, @ceil)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; min/max
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; There is no blend instruction with SSE2, so we simulate it with bit
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; operations on i32s. For these two vselect functions, for each
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; vector element, if the mask is on, we return the corresponding value
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; from %1, and otherwise return the value from %0.
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define <4 x i32> @__vselect_i32(<4 x i32>, <4 x i32> ,
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<4 x i32> %mask) nounwind readnone alwaysinline {
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%cleared_old = and <4 x i32> %0, %notmask
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%masked_new = and <4 x i32> %1, %mask
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%new = or <4 x i32> %cleared_old, %masked_new
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ret <4 x i32> %new
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}
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define <4 x float> @__vselect_float(<4 x float>, <4 x float>,
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<4 x i32> %mask) nounwind readnone alwaysinline {
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%v0 = bitcast <4 x float> %0 to <4 x i32>
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%v1 = bitcast <4 x float> %1 to <4 x i32>
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%r = call <4 x i32> @__vselect_i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %mask)
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%rf = bitcast <4 x i32> %r to <4 x float>
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ret <4 x float> %rf
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}
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; To do vector integer min and max, we do the vector compare and then sign
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; extend the i1 vector result to an i32 mask. The __vselect does the
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; rest...
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define <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp slt <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp slt i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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define <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp sgt <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp sgt i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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; The functions for unsigned ints are similar, just with unsigned
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; comparison functions...
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define <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp ult <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp ult i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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define <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp ugt <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp ugt i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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define i64 @__movmsk(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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%v64 = zext i32 %v to i64
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ret i64 %v64
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}
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define i1 @__any(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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%cmp = icmp ne i32 %v, 0
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ret i1 %cmp
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}
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define i1 @__all(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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%cmp = icmp eq i32 %v, 15
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ret i1 %cmp
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}
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define i1 @__none(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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%cmp = icmp eq i32 %v, 0
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ret i1 %cmp
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}
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declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
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define i16 @__reduce_add_int8(<4 x i8>) nounwind readnone alwaysinline {
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%wide8 = shufflevector <4 x i8> %0, <4 x i8> zeroinitializer,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4,
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i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
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%rv = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %wide8,
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<16 x i8> zeroinitializer)
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%r0 = extractelement <2 x i64> %rv, i32 0
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%r1 = extractelement <2 x i64> %rv, i32 1
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%r = add i64 %r0, %r1
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%r16 = trunc i64 %r to i16
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ret i16 %r16
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}
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define internal <4 x i16> @__add_varying_i16(<4 x i16>,
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<4 x i16>) nounwind readnone alwaysinline {
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%r = add <4 x i16> %0, %1
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ret <4 x i16> %r
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}
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define internal i16 @__add_uniform_i16(i16, i16) nounwind readnone alwaysinline {
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%r = add i16 %0, %1
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ret i16 %r
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}
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define i16 @__reduce_add_int16(<4 x i16>) nounwind readnone alwaysinline {
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reduce4(i16, @__add_varying_i16, @__add_uniform_i16)
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}
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define float @__reduce_add_float(<4 x float> %v) nounwind readonly alwaysinline {
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%v1 = shufflevector <4 x float> %v, <4 x float> undef,
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<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%m1 = fadd <4 x float> %v1, %v
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%m1a = extractelement <4 x float> %m1, i32 0
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%m1b = extractelement <4 x float> %m1, i32 1
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%sum = fadd float %m1a, %m1b
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ret float %sum
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}
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define float @__reduce_min_float(<4 x float>) nounwind readnone {
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reduce4(float, @__min_varying_float, @__min_uniform_float)
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}
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define float @__reduce_max_float(<4 x float>) nounwind readnone {
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reduce4(float, @__max_varying_float, @__max_uniform_float)
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}
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define i32 @__reduce_add_int32(<4 x i32> %v) nounwind readnone {
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%v1 = shufflevector <4 x i32> %v, <4 x i32> undef,
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<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%m1 = add <4 x i32> %v1, %v
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%m1a = extractelement <4 x i32> %m1, i32 0
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%m1b = extractelement <4 x i32> %m1, i32 1
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%sum = add i32 %m1a, %m1b
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ret i32 %sum
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}
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define i32 @__reduce_min_int32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__min_varying_int32, @__min_uniform_int32)
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}
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define i32 @__reduce_max_int32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__max_varying_int32, @__max_uniform_int32)
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}
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define i32 @__reduce_min_uint32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__min_varying_uint32, @__min_uniform_uint32)
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}
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define i32 @__reduce_max_uint32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__max_varying_uint32, @__max_uniform_uint32)
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}
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define double @__reduce_add_double(<4 x double>) nounwind readnone {
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%v0 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 2, i32 3>
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%sum = fadd <2 x double> %v0, %v1
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%e0 = extractelement <2 x double> %sum, i32 0
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%e1 = extractelement <2 x double> %sum, i32 1
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%m = fadd double %e0, %e1
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ret double %m
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}
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define double @__reduce_min_double(<4 x double>) nounwind readnone {
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reduce4(double, @__min_varying_double, @__min_uniform_double)
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}
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define double @__reduce_max_double(<4 x double>) nounwind readnone {
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reduce4(double, @__max_varying_double, @__max_uniform_double)
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}
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define i64 @__reduce_add_int64(<4 x i64>) nounwind readnone {
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%v0 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%sum = add <2 x i64> %v0, %v1
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%e0 = extractelement <2 x i64> %sum, i32 0
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%e1 = extractelement <2 x i64> %sum, i32 1
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%m = add i64 %e0, %e1
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ret i64 %m
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}
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define i64 @__reduce_min_int64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__min_varying_int64, @__min_uniform_int64)
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}
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define i64 @__reduce_max_int64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__max_varying_int64, @__max_uniform_int64)
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}
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define i64 @__reduce_min_uint64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__min_varying_uint64, @__min_uniform_uint64)
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}
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define i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone {
|
|
reduce4(i64, @__max_varying_uint64, @__max_uniform_uint64)
|
|
}
|
|
|
|
reduce_equal(4)
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; masked store
|
|
|
|
define void @__masked_store_blend_i32(<4 x i32>* nocapture, <4 x i32>,
|
|
<4 x i32> %mask) nounwind alwaysinline {
|
|
%val = load PTR_OP_ARGS(`<4 x i32> ') %0, align 4
|
|
%newval = call <4 x i32> @__vselect_i32(<4 x i32> %val, <4 x i32> %1, <4 x i32> %mask)
|
|
store <4 x i32> %newval, <4 x i32> * %0, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @__masked_store_blend_i64(<4 x i64>* nocapture %ptr, <4 x i64> %new,
|
|
<4 x i32> %mask) nounwind alwaysinline {
|
|
%oldValue = load PTR_OP_ARGS(`<4 x i64>') %ptr, align 8
|
|
|
|
; Do 4x64-bit blends by doing two <4 x i32> blends, where the <4 x i32> values
|
|
; are actually bitcast <2 x i64> values
|
|
;
|
|
; set up the first two 64-bit values
|
|
%old01 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
|
|
<2 x i32> <i32 0, i32 1>
|
|
%old01f = bitcast <2 x i64> %old01 to <4 x float>
|
|
%new01 = shufflevector <4 x i64> %new, <4 x i64> undef,
|
|
<2 x i32> <i32 0, i32 1>
|
|
%new01f = bitcast <2 x i64> %new01 to <4 x float>
|
|
; compute mask--note that the indices 0 and 1 are doubled-up
|
|
%mask01 = shufflevector <4 x i32> %mask, <4 x i32> undef,
|
|
<4 x i32> <i32 0, i32 0, i32 1, i32 1>
|
|
; and blend the two of the values
|
|
%result01f = call <4 x float> @__vselect_float(<4 x float> %old01f, <4 x float> %new01f, <4 x i32> %mask01)
|
|
%result01 = bitcast <4 x float> %result01f to <2 x i64>
|
|
|
|
; and again
|
|
%old23 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
|
|
<2 x i32> <i32 2, i32 3>
|
|
%old23f = bitcast <2 x i64> %old23 to <4 x float>
|
|
%new23 = shufflevector <4 x i64> %new, <4 x i64> undef,
|
|
<2 x i32> <i32 2, i32 3>
|
|
%new23f = bitcast <2 x i64> %new23 to <4 x float>
|
|
; compute mask--note that the values 2 and 3 are doubled-up
|
|
%mask23 = shufflevector <4 x i32> %mask, <4 x i32> undef,
|
|
<4 x i32> <i32 2, i32 2, i32 3, i32 3>
|
|
; and blend the two of the values
|
|
%result23f = call <4 x float> @__vselect_float(<4 x float> %old23f, <4 x float> %new23f, <4 x i32> %mask23)
|
|
%result23 = bitcast <4 x float> %result23f to <2 x i64>
|
|
|
|
; reconstruct the final <4 x i64> vector
|
|
%final = shufflevector <2 x i64> %result01, <2 x i64> %result23,
|
|
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
store <4 x i64> %final, <4 x i64> * %ptr, align 8
|
|
ret void
|
|
}
|
|
|
|
|
|
masked_store_float_double()
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; rcp
|
|
|
|
declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
|
|
|
|
define <4 x float> @__rcp_varying_float(<4 x float>) nounwind readonly alwaysinline {
|
|
%call = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %0)
|
|
; do one N-R iteration to improve precision
|
|
; float iv = __rcp_v(v);
|
|
; return iv * (2. - v * iv);
|
|
%v_iv = fmul <4 x float> %0, %call
|
|
%two_minus = fsub <4 x float> <float 2., float 2., float 2., float 2.>, %v_iv
|
|
%iv_mul = fmul <4 x float> %call, %two_minus
|
|
ret <4 x float> %iv_mul
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
; rsqrt
|
|
|
|
declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
|
|
|
|
define <4 x float> @__rsqrt_varying_float(<4 x float> %v) nounwind readonly alwaysinline {
|
|
; float is = __rsqrt_v(v);
|
|
%is = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %v)
|
|
; Newton-Raphson iteration to improve precision
|
|
; return 0.5 * is * (3. - (v * is) * is);
|
|
%v_is = fmul <4 x float> %v, %is
|
|
%v_is_is = fmul <4 x float> %v_is, %is
|
|
%three_sub = fsub <4 x float> <float 3., float 3., float 3., float 3.>, %v_is_is
|
|
%is_mul = fmul <4 x float> %is, %three_sub
|
|
%half_scale = fmul <4 x float> <float 0.5, float 0.5, float 0.5, float 0.5>, %is_mul
|
|
ret <4 x float> %half_scale
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
; sqrt
|
|
|
|
declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
|
|
|
|
define <4 x float> @__sqrt_varying_float(<4 x float>) nounwind readonly alwaysinline {
|
|
%call = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %0)
|
|
ret <4 x float> %call
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
; svml stuff
|
|
|
|
include(`svml.m4')
|
|
;; single precision
|
|
svml_declare(float,f4,4)
|
|
svml_define(float,f4,4,f)
|
|
|
|
;; double precision
|
|
svml_declare(double,2,2)
|
|
svml_define_x(double,2,2,d,4)
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; float min/max
|
|
|
|
declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
define <4 x float> @__max_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
|
|
%call = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %0, <4 x float> %1)
|
|
ret <4 x float> %call
|
|
}
|
|
|
|
define <4 x float> @__min_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
|
|
%call = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %0, <4 x float> %1)
|
|
ret <4 x float> %call
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; double precision sqrt
|
|
|
|
declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
|
|
|
|
define <4 x double> @__sqrt_varying_double(<4 x double>) nounwind alwaysinline {
|
|
unary2to4(ret, double, @llvm.x86.sse2.sqrt.pd, %0)
|
|
ret <4 x double> %ret
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; double precision min/max
|
|
|
|
declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
define <4 x double> @__min_varying_double(<4 x double>, <4 x double>) nounwind readnone {
|
|
binary2to4(ret, double, @llvm.x86.sse2.min.pd, %0, %1)
|
|
ret <4 x double> %ret
|
|
}
|
|
|
|
define <4 x double> @__max_varying_double(<4 x double>, <4 x double>) nounwind readnone {
|
|
binary2to4(ret, double, @llvm.x86.sse2.max.pd, %0, %1)
|
|
ret <4 x double> %ret
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; masked store
|
|
|
|
masked_store_blend_8_16_by_4()
|
|
|
|
gen_masked_store(i8)
|
|
gen_masked_store(i16)
|
|
gen_masked_store(i32)
|
|
gen_masked_store(i64)
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; unaligned loads/loads+broadcasts
|
|
|
|
|
|
masked_load(i8, 1)
|
|
masked_load(i16, 2)
|
|
masked_load(i32, 4)
|
|
masked_load(float, 4)
|
|
masked_load(i64, 8)
|
|
masked_load(double, 8)
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; gather/scatter
|
|
|
|
; define these with the macros from stdlib.m4
|
|
|
|
gen_gather_factored(i8)
|
|
gen_gather_factored(i16)
|
|
gen_gather_factored(i32)
|
|
gen_gather_factored(float)
|
|
gen_gather_factored(i64)
|
|
gen_gather_factored(double)
|
|
|
|
gen_scatter(i8)
|
|
gen_scatter(i16)
|
|
gen_scatter(i32)
|
|
gen_scatter(float)
|
|
gen_scatter(i64)
|
|
gen_scatter(double)
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; reciprocals in double precision, if supported
|
|
|
|
rsqrtd_decl()
|
|
rcpd_decl()
|
|
|
|
transcendetals_decl()
|
|
trigonometry_decl()
|