5a53a43ed0
Add much more suppport for doubles and in64 types in the standard library, basically supporting everything for them that are supported for floats and int32s. (The notable exceptions being the approximate rcp() and rsqrt() functions, which don't really have sensible analogs for doubles (or at least not built-in instructions).)
381 lines
15 KiB
LLVM
381 lines
15 KiB
LLVM
;; Copyright (c) 2010-2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Define the standard library builtins for the SSE2 target
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; Define some basics for a 4-wide target
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stdlib_core(4)
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packed_load_and_store(4)
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; Include the various definitions of things that only require SSE1 and SSE2
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include(`stdlib-sse.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding
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;;
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;; There are not any rounding instructions in SSE2, so we have to emulate
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;; the functionality with multiple instructions...
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; The code for __round_* is the result of compiling the following source
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; code.
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;
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; export float Round(float x) {
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; unsigned int sign = signbits(x);
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; unsigned int ix = intbits(x);
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; ix ^= sign;
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; x = floatbits(ix);
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; x += 0x1.0p23f;
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; x -= 0x1.0p23f;
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; ix = intbits(x);
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; ix ^= sign;
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; x = floatbits(ix);
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; return x;
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;}
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define internal <4 x float> @__round_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%float_to_int_bitcast.i.i.i.i = bitcast <4 x float> %0 to <4 x i32>
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%bitop.i.i = and <4 x i32> %float_to_int_bitcast.i.i.i.i, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%bitop.i = xor <4 x i32> %float_to_int_bitcast.i.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i40.i = bitcast <4 x i32> %bitop.i to <4 x float>
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%binop.i = fadd <4 x float> %int_to_float_bitcast.i.i40.i, <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>
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%binop21.i = fadd <4 x float> %binop.i, <float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06>
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%float_to_int_bitcast.i.i.i = bitcast <4 x float> %binop21.i to <4 x i32>
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%bitop31.i = xor <4 x i32> %float_to_int_bitcast.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i.i = bitcast <4 x i32> %bitop31.i to <4 x float>
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ret <4 x float> %int_to_float_bitcast.i.i.i
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}
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define internal float @__round_uniform_float(float) nounwind readonly alwaysinline {
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%float_to_int_bitcast.i.i.i.i = bitcast float %0 to i32
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%bitop.i.i = and i32 %float_to_int_bitcast.i.i.i.i, -2147483648
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%bitop.i = xor i32 %bitop.i.i, %float_to_int_bitcast.i.i.i.i
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%int_to_float_bitcast.i.i40.i = bitcast i32 %bitop.i to float
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%binop.i = fadd float %int_to_float_bitcast.i.i40.i, 8.388608e+06
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%binop21.i = fadd float %binop.i, -8.388608e+06
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%float_to_int_bitcast.i.i.i = bitcast float %binop21.i to i32
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%bitop31.i = xor i32 %float_to_int_bitcast.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i.i = bitcast i32 %bitop31.i to float
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ret float %int_to_float_bitcast.i.i.i
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}
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;; Similarly, for implementations of the __floor* functions below, we have the
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;; bitcode from compiling the following source code...
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;export float Floor(float x) {
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; float y = Round(x);
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; unsigned int cmp = y > x ? 0xffffffff : 0;
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; float delta = -1.f;
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; unsigned int idelta = intbits(delta);
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; idelta &= cmp;
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; delta = floatbits(idelta);
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; return y + delta;
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;}
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define internal <4 x float> @__floor_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <4 x float> @__round_varying_float(<4 x float> %0) nounwind
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%bincmp.i = fcmp ogt <4 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <4 x i1> %bincmp.i to <4 x i32>
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%bitop.i = and <4 x i32> %val_to_boolvec32.i, <i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432>
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%int_to_float_bitcast.i.i.i = bitcast <4 x i32> %bitop.i to <4 x float>
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%binop.i = fadd <4 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <4 x float> %binop.i
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}
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define internal float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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%calltmp.i = tail call float @__round_uniform_float(float %0) nounwind
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%bincmp.i = fcmp ogt float %calltmp.i, %0
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%selectexpr.i = sext i1 %bincmp.i to i32
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%bitop.i = and i32 %selectexpr.i, -1082130432
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%int_to_float_bitcast.i.i.i = bitcast i32 %bitop.i to float
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%binop.i = fadd float %calltmp.i, %int_to_float_bitcast.i.i.i
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ret float %binop.i
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}
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;; And here is the code we compiled to get the __ceil* functions below
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;
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;export uniform float Ceil(uniform float x) {
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; uniform float y = Round(x);
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; uniform int yltx = y < x ? 0xffffffff : 0;
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; uniform float delta = 1.f;
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; uniform int idelta = intbits(delta);
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; idelta &= yltx;
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; delta = floatbits(idelta);
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; return y + delta;
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;}
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define internal <4 x float> @__ceil_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <4 x float> @__round_varying_float(<4 x float> %0) nounwind
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%bincmp.i = fcmp olt <4 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <4 x i1> %bincmp.i to <4 x i32>
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%bitop.i = and <4 x i32> %val_to_boolvec32.i, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
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%int_to_float_bitcast.i.i.i = bitcast <4 x i32> %bitop.i to <4 x float>
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%binop.i = fadd <4 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <4 x float> %binop.i
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}
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define internal float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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%calltmp.i = tail call float @__round_uniform_float(float %0) nounwind
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%bincmp.i = fcmp olt float %calltmp.i, %0
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%selectexpr.i = sext i1 %bincmp.i to i32
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%bitop.i = and i32 %selectexpr.i, 1065353216
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%int_to_float_bitcast.i.i.i = bitcast i32 %bitop.i to float
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%binop.i = fadd float %calltmp.i, %int_to_float_bitcast.i.i.i
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ret float %binop.i
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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declare double @round(double)
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declare double @floor(double)
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declare double @ceil(double)
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define internal <4 x double> @__round_varying_double(<4 x double>) nounwind readonly alwaysinline {
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unary1to4(double, @round)
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}
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define internal double @__round_uniform_double(double) nounwind readonly alwaysinline {
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%r = call double @round(double %0)
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ret double %r
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}
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define internal <4 x double> @__floor_varying_double(<4 x double>) nounwind readonly alwaysinline {
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unary1to4(double, @floor)
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}
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define internal double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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%r = call double @floor(double %0)
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ret double %r
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}
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define internal <4 x double> @__ceil_varying_double(<4 x double>) nounwind readonly alwaysinline {
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unary1to4(double, @ceil)
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}
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define internal double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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%r = call double @ceil(double %0)
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ret double %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; min/max
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; There is no blend instruction with SSE2, so we simulate it with bit
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; operations on i32s. For these two vselect functions, for each
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; vector element, if the mask is on, we return the corresponding value
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; from %1, and otherwise return the value from %0.
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define internal <4 x i32> @__vselect_i32(<4 x i32>, <4 x i32> ,
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<4 x i32> %mask) nounwind readnone alwaysinline {
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%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
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%cleared_old = and <4 x i32> %0, %notmask
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%masked_new = and <4 x i32> %1, %mask
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%new = or <4 x i32> %cleared_old, %masked_new
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ret <4 x i32> %new
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}
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define internal <4 x float> @__vselect_float(<4 x float>, <4 x float>,
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<4 x i32> %mask) nounwind readnone alwaysinline {
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%v0 = bitcast <4 x float> %0 to <4 x i32>
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%v1 = bitcast <4 x float> %1 to <4 x i32>
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%r = call <4 x i32> @__vselect_i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %mask)
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%rf = bitcast <4 x i32> %r to <4 x float>
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ret <4 x float> %rf
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}
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; To do vector integer min and max, we do the vector compare and then sign
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; extend the i1 vector result to an i32 mask. The __vselect does the
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; rest...
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define internal <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp slt <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define internal i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp slt i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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define internal <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp sgt <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define internal i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp sgt i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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; The functions for unsigned ints are similar, just with unsigned
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; comparison functions...
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define internal <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp ult <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define internal i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp ult i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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define internal <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%c = icmp ugt <4 x i32> %0, %1
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%mask = sext <4 x i1> %c to <4 x i32>
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%v = call <4 x i32> @__vselect_i32(<4 x i32> %1, <4 x i32> %0, <4 x i32> %mask)
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ret <4 x i32> %v
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}
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define internal i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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%c = icmp ugt i32 %0, %1
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%r = select i1 %c, i32 %0, i32 %1
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ret i32 %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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; FIXME: this is very inefficient, loops over all 32 bits...
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; we could use the LLVM intrinsic declare i32 @llvm.ctpop.i32(i32),
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; although that currently ends up generating a POPCNT instruction even
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; if we give --target=sse2 on the command line. We probably need to
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; pipe through the 'sse2' request to LLVM via the 'features' string
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; at codegen time... (If e.g. --cpu=penryn is also passed along, then
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; it does generate non-POPCNT code and in particular better code than
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; the below does.)
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define internal i32 @__popcnt_int32(i32) nounwind readonly alwaysinline {
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entry:
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br label %loop
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loop:
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%count = phi i32 [ 0, %entry ], [ %newcount, %loop ]
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%val = phi i32 [ %0, %entry ], [ %newval, %loop ]
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%delta = and i32 %val, 1
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%newcount = add i32 %count, %delta
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%newval = lshr i32 %val, 1
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%done = icmp eq i32 %newval, 0
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br i1 %done, label %exit, label %loop
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exit:
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ret i32 %newcount
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}
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define internal i32 @__popcnt_int64(i64) nounwind readnone alwaysinline {
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%vec = bitcast i64 %0 to <2 x i32>
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%v0 = extractelement <2 x i32> %vec, i32 0
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%v1 = extractelement <2 x i32> %vec, i32 1
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%c0 = call i32 @__popcnt_int32(i32 %v0)
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%c1 = call i32 @__popcnt_int32(i32 %v1)
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%sum = add i32 %c0, %c1
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ret i32 %sum
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}
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define internal float @__reduce_add_float(<4 x float> %v) nounwind readonly alwaysinline {
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%v1 = shufflevector <4 x float> %v, <4 x float> undef,
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<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%m1 = fadd <4 x float> %v1, %v
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%m1a = extractelement <4 x float> %m1, i32 0
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%m1b = extractelement <4 x float> %m1, i32 1
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%sum = fadd float %m1a, %m1b
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ret float %sum
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
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define void @__masked_store_blend_32(<4 x i32>* nocapture, <4 x i32>,
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<4 x i32> %mask) nounwind alwaysinline {
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%val = load <4 x i32> * %0, align 4
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%newval = call <4 x i32> @__vselect_i32(<4 x i32> %val, <4 x i32> %1, <4 x i32> %mask)
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store <4 x i32> %newval, <4 x i32> * %0, align 4
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ret void
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}
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define void @__masked_store_blend_64(<4 x i64>* nocapture %ptr, <4 x i64> %new,
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<4 x i32> %mask) nounwind alwaysinline {
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%oldValue = load <4 x i64>* %ptr, align 8
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; Do 4x64-bit blends by doing two <4 x i32> blends, where the <4 x i32> values
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; are actually bitcast <2 x i64> values
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;
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; set up the first two 64-bit values
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%old01 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%old01f = bitcast <2 x i64> %old01 to <4 x float>
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%new01 = shufflevector <4 x i64> %new, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%new01f = bitcast <2 x i64> %new01 to <4 x float>
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; compute mask--note that the indices 0 and 1 are doubled-up
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%mask01 = shufflevector <4 x i32> %mask, <4 x i32> undef,
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<4 x i32> <i32 0, i32 0, i32 1, i32 1>
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; and blend the two of the values
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%result01f = call <4 x float> @__vselect_float(<4 x float> %old01f, <4 x float> %new01f, <4 x i32> %mask01)
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%result01 = bitcast <4 x float> %result01f to <2 x i64>
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; and again
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%old23 = shufflevector <4 x i64> %oldValue, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%old23f = bitcast <2 x i64> %old23 to <4 x float>
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%new23 = shufflevector <4 x i64> %new, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%new23f = bitcast <2 x i64> %new23 to <4 x float>
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; compute mask--note that the values 2 and 3 are doubled-up
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%mask23 = shufflevector <4 x i32> %mask, <4 x i32> undef,
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<4 x i32> <i32 2, i32 2, i32 3, i32 3>
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; and blend the two of the values
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%result23f = call <4 x float> @__vselect_float(<4 x float> %old23f, <4 x float> %new23f, <4 x i32> %mask23)
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%result23 = bitcast <4 x float> %result23f to <2 x i64>
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; reconstruct the final <4 x i64> vector
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%final = shufflevector <2 x i64> %result01, <2 x i64> %result23,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i64> %final, <4 x i64> * %ptr, align 8
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ret void
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}
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