6c7df4cb6b
So far, only the use of the float/half conversion instructions distinguishes this from the "avx1" target. Partial work on issue #263.
163 lines
6.6 KiB
LLVM
163 lines
6.6 KiB
LLVM
;; Copyright (c) 2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;; This file defines various functions that are used when generating the
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;; the "dispatch" object/assembly file that has entrypoints for each
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;; exported function in a module that dispatch to the best available
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;; variant of that function that will run on the system's CPU.
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;; Stores the best target ISA that the system on which we're actually
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;; running supports. -1 represents "uninitialized", otherwise this value
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;; should correspond to one of the enumerant values of Target::ISA from
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;; ispc.h.
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@__system_best_isa = internal global i32 -1
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declare void @abort() noreturn
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;; The below is the result of running "clang -O2 -emit-llvm -c -o -" on the
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;; following code... Specifically, __get_system_isa should return a value
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;; corresponding to one of the Target::ISA enumerant values that gives the
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;; most capable ISA that the curremt system can run.
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;;
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;; Note: clang from LLVM 3.0 should be used if this is updated, for maximum
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;; backwards compatibility for anyone building ispc with LLVM 3.0
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;;
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;; #include <stdint.h>
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;; #include <stdlib.h>
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;;
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;; static void __cpuid(int info[4], int infoType) {
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;; __asm__ __volatile__ ("cpuid"
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;; : "=a" (info[0]), "=b" (info[1]), "=c" (info[2]), "=d" (info[3])
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;; : "0" (infoType));
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;; }
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;;
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;; /* Save %ebx in case it's the PIC register */
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;; static void __cpuid_count(int info[4], int level, int count) {
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;; __asm__ __volatile__ ("xchg{l}\t{%%}ebx, %1\n\t"
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;; "cpuid\n\t"
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;; "xchg{l}\t{%%}ebx, %1\n\t"
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;; : "=a" (info[0]), "=r" (info[1]), "=c" (info[2]), "=d" (info[3])
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;; : "0" (level), "2" (count));
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;; }
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;;
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;; int32_t __get_system_isa() {
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;; int info[4];
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;; __cpuid(info, 1);
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;;
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;; /* NOTE: the values returned below must be the same as the
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;; corresponding enumerant values in Target::ISA. */
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;; if ((info[2] & (1 << 28)) != 0) {
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;; // AVX1 for sure. Do we have AVX2?
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;; // Call cpuid with eax=7, ecx=0
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;; __cpuid_count(info, 7, 0);
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;; if ((info[1] & (1 << 5)) != 0)
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;; return 4; // AVX2
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;; else {
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;; if ((info[2] & (1 << 29)) != 0 && // F16C
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;; (info[2] & (1 << 30)) != 0) // RDRAND
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;; return 3; // AVX1 on IVB
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;; else
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;; return 2; // AVX1
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;; }
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;; }
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;; else if ((info[2] & (1 << 19)) != 0)
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;; return 1; // SSE4
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;; else if ((info[3] & (1 << 26)) != 0)
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;; return 0; // SSE2
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;; else
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;; abort();
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;; }
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define i32 @__get_system_isa() nounwind uwtable ssp {
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entry:
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%0 = tail call { i32, i32, i32, i32 } asm sideeffect "cpuid", "={ax},={bx},={cx},={dx},0,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
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%asmresult5.i = extractvalue { i32, i32, i32, i32 } %0, 2
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%asmresult6.i = extractvalue { i32, i32, i32, i32 } %0, 3
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%and = and i32 %asmresult5.i, 268435456
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%cmp = icmp eq i32 %and, 0
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br i1 %cmp, label %if.else14, label %if.then
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if.then: ; preds = %entry
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%1 = tail call { i32, i32, i32, i32 } asm sideeffect "xchg$(l$)\09$(%$)ebx, $1\0A\09cpuid\0A\09xchg$(l$)\09$(%$)ebx, $1\0A\09", "={ax},=r,={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}"(i32 7, i32 0) nounwind
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%asmresult4.i29 = extractvalue { i32, i32, i32, i32 } %1, 1
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%and3 = and i32 %asmresult4.i29, 32
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%cmp4 = icmp eq i32 %and3, 0
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br i1 %cmp4, label %if.else, label %return
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if.else: ; preds = %if.then
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%asmresult5.i30 = extractvalue { i32, i32, i32, i32 } %1, 2
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%2 = and i32 %asmresult5.i30, 1610612736
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%3 = icmp eq i32 %2, 1610612736
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br i1 %3, label %return, label %if.else13
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if.else13: ; preds = %if.else
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br label %return
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if.else14: ; preds = %entry
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%and16 = and i32 %asmresult5.i, 524288
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%cmp17 = icmp eq i32 %and16, 0
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br i1 %cmp17, label %if.else19, label %return
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if.else19: ; preds = %if.else14
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%and21 = and i32 %asmresult6.i, 67108864
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%cmp22 = icmp eq i32 %and21, 0
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br i1 %cmp22, label %if.else24, label %return
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if.else24: ; preds = %if.else19
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tail call void @abort() noreturn nounwind
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unreachable
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return: ; preds = %if.else19, %if.else14, %if.else13, %if.else, %if.then
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%retval.0 = phi i32 [ 2, %if.else13 ], [ 4, %if.then ], [ 3, %if.else ], [ 1, %if.else14 ], [ 0, %if.else19 ]
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ret i32 %retval.0
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; This function is called by each of the dispatch functions we generate;
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;; it sets @__system_best_isa if it is unset.
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define void @__set_system_isa() {
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entry:
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%bi = load i32* @__system_best_isa
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%unset = icmp eq i32 %bi, -1
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br i1 %unset, label %set_system_isa, label %done
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set_system_isa:
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%bival = call i32 @__get_system_isa()
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store i32 %bival, i32* @__system_best_isa
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ret void
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done:
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ret void
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}
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