e156651190
Fixed the implementations of these builtin functions for targets that don't have native masked load instructions so that they do no loads if the vector mask is all off, and only do an (unaligned) vector load if both the first and last element of the mask are on. Otherwise they serialize and do scalar loads for only the active lanes. This fixes a number of potential sources of crashes due to accessing invalid memory.
418 lines
15 KiB
LLVM
418 lines
15 KiB
LLVM
;; Copyright (c) 2010-2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;; This file declares implementations of various stdlib builtins that
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;; only require SSE version 1 and 2 functionality; this file, in turn
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;; is then included by stdlib-sse2.ll and stdlib-sse4.ll to provide
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;; those definitions for them.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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int8_16(4)
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int64minmax(4)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define internal <4 x float> @__rcp_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %0)
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; do one N-R iteration to improve precision
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; float iv = __rcp_v(v);
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; return iv * (2. - v * iv);
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%v_iv = fmul <4 x float> %0, %call
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%two_minus = fsub <4 x float> <float 2., float 2., float 2., float 2.>, %v_iv
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%iv_mul = fmul <4 x float> %call, %two_minus
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ret <4 x float> %iv_mul
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}
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define internal float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; do the rcpss call
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%vecval = insertelement <4 x float> undef, float %0, i32 0
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%call = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecval)
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%scall = extractelement <4 x float> %call, i32 0
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; do one N-R iteration to improve precision, as above
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%v_iv = fmul float %0, %scall
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%two_minus = fsub float 2., %v_iv
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%iv_mul = fmul float %scall, %two_minus
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ret float %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; rsqrt
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declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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define internal <4 x float> @__rsqrt_varying_float(<4 x float> %v) nounwind readonly alwaysinline {
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; float is = __rsqrt_v(v);
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%is = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %v)
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul <4 x float> %v, %is
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%v_is_is = fmul <4 x float> %v_is, %is
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%three_sub = fsub <4 x float> <float 3., float 3., float 3., float 3.>, %v_is_is
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%is_mul = fmul <4 x float> %is, %three_sub
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%half_scale = fmul <4 x float> <float 0.5, float 0.5, float 0.5, float 0.5>, %is_mul
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ret <4 x float> %half_scale
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}
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define internal float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
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; uniform float is = extract(__rsqrt_u(v), 0);
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%v = insertelement <4 x float> undef, float %0, i32 0
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%vis = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %v)
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%is = extractelement <4 x float> %vis, i32 0
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul float %0, %is
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%v_is_is = fmul float %v_is, %is
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%three_sub = fsub float 3., %v_is_is
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%is_mul = fmul float %is, %three_sub
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%half_scale = fmul float 0.5, %is_mul
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ret float %half_scale
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; sqrt
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declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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define internal <4 x float> @__sqrt_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %0)
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ret <4 x float> %call
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}
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define internal float @__sqrt_uniform_float(float) nounwind readonly alwaysinline {
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sse_unary_scalar(ret, 4, float, @llvm.x86.sse.sqrt.ss, %0)
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; fast math mode
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declare void @llvm.x86.sse.stmxcsr(i32 *) nounwind
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declare void @llvm.x86.sse.ldmxcsr(i32 *) nounwind
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define internal void @__fastmath() nounwind alwaysinline {
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%ptr = alloca i32
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call void @llvm.x86.sse.stmxcsr(i32 * %ptr)
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%oldval = load i32 *%ptr
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; turn on DAZ (64)/FTZ (32768) -> 32832
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%update = or i32 %oldval, 32832
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store i32 %update, i32 *%ptr
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call void @llvm.x86.sse.ldmxcsr(i32 * %ptr)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; svml stuff
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declare <4 x float> @__svml_sinf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_cosf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_sincosf4(<4 x float> *, <4 x float>) nounwind readnone
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declare <4 x float> @__svml_tanf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_atanf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_atan2f4(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @__svml_expf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_logf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_powf4(<4 x float>, <4 x float>) nounwind readnone
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define internal <4 x float> @__svml_sin(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_sinf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_cos(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_cosf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal void @__svml_sincos(<4 x float>, <4 x float> *, <4 x float> *) nounwind readnone alwaysinline {
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%s = call <4 x float> @__svml_sincosf4(<4 x float> * %2, <4 x float> %0)
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store <4 x float> %s, <4 x float> * %1
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ret void
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}
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define internal <4 x float> @__svml_tan(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_tanf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_atan(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_atanf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_atan2(<4 x float>, <4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_atan2f4(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_exp(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_expf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_log(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_logf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_pow(<4 x float>, <4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_powf4(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
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define internal <4 x float> @__max_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %call
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}
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define internal float @__max_uniform_float(float, float) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, float, @llvm.x86.sse.max.ss, %0, %1)
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ret float %ret
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}
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define internal <4 x float> @__min_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %call
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}
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define internal float @__min_uniform_float(float, float) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, float, @llvm.x86.sse.min.ss, %0, %1)
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define internal <4 x double> @__sqrt_varying_double(<4 x double>) nounwind alwaysinline {
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unary2to4(ret, double, @llvm.x86.sse2.sqrt.pd, %0)
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ret <4 x double> %ret
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}
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define internal double @__sqrt_uniform_double(double) nounwind alwaysinline {
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sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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define internal <4 x double> @__min_varying_double(<4 x double>, <4 x double>) nounwind readnone {
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binary2to4(ret, double, @llvm.x86.sse2.min.pd, %0, %1)
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ret <4 x double> %ret
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}
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define internal double @__min_uniform_double(double, double) nounwind readnone {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.min.sd, %0, %1)
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ret double %ret
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}
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define internal <4 x double> @__max_varying_double(<4 x double>, <4 x double>) nounwind readnone {
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binary2to4(ret, double, @llvm.x86.sse2.max.pd, %0, %1)
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ret <4 x double> %ret
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}
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define internal double @__max_uniform_double(double, double) nounwind readnone {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.max.sd, %0, %1)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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define internal i32 @__movmsk(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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ret i32 %v
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}
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define internal float @__reduce_min_float(<4 x float>) nounwind readnone {
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reduce4(float, @__min_varying_float, @__min_uniform_float)
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}
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define internal float @__reduce_max_float(<4 x float>) nounwind readnone {
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reduce4(float, @__max_varying_float, @__max_uniform_float)
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}
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define internal i32 @__reduce_add_int32(<4 x i32> %v) nounwind readnone {
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%v1 = shufflevector <4 x i32> %v, <4 x i32> undef,
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<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%m1 = add <4 x i32> %v1, %v
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%m1a = extractelement <4 x i32> %m1, i32 0
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%m1b = extractelement <4 x i32> %m1, i32 1
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%sum = add i32 %m1a, %m1b
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ret i32 %sum
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}
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define internal i32 @__reduce_min_int32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__min_varying_int32, @__min_uniform_int32)
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}
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define internal i32 @__reduce_max_int32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__max_varying_int32, @__max_uniform_int32)
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}
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define internal i32 @__reduce_add_uint32(<4 x i32> %v) nounwind readnone {
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%r = call i32 @__reduce_add_int32(<4 x i32> %v)
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ret i32 %r
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}
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define internal i32 @__reduce_min_uint32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__min_varying_uint32, @__min_uniform_uint32)
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}
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define internal i32 @__reduce_max_uint32(<4 x i32>) nounwind readnone {
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reduce4(i32, @__max_varying_uint32, @__max_uniform_uint32)
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}
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define internal double @__reduce_add_double(<4 x double>) nounwind readnone {
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%v0 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 2, i32 3>
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%sum = fadd <2 x double> %v0, %v1
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%e0 = extractelement <2 x double> %sum, i32 0
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%e1 = extractelement <2 x double> %sum, i32 1
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%m = fadd double %e0, %e1
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ret double %m
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}
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define internal double @__reduce_min_double(<4 x double>) nounwind readnone {
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reduce4(double, @__min_varying_double, @__min_uniform_double)
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}
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define internal double @__reduce_max_double(<4 x double>) nounwind readnone {
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reduce4(double, @__max_varying_double, @__max_uniform_double)
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}
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define internal i64 @__reduce_add_int64(<4 x i64>) nounwind readnone {
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%v0 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 2, i32 3>
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%sum = add <2 x i64> %v0, %v1
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%e0 = extractelement <2 x i64> %sum, i32 0
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%e1 = extractelement <2 x i64> %sum, i32 1
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%m = add i64 %e0, %e1
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ret i64 %m
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}
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define internal i64 @__reduce_min_int64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__min_varying_int64, @__min_uniform_int64)
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}
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define internal i64 @__reduce_max_int64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__max_varying_int64, @__max_uniform_int64)
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}
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define internal i64 @__reduce_min_uint64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__min_varying_uint64, @__min_uniform_uint64)
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}
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define internal i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone {
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reduce4(i64, @__max_varying_uint64, @__max_uniform_uint64)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; masked store
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define void @__masked_store_32(<4 x i32>* nocapture, <4 x i32>, <4 x i32>) nounwind alwaysinline {
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per_lane(4, <4 x i32> %2, `
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; compute address for this one
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%ptr_ID = getelementptr <4 x i32> * %0, i32 0, i32 LANE
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%storeval_ID = extractelement <4 x i32> %1, i32 LANE
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store i32 %storeval_ID, i32 * %ptr_ID')
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ret void
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}
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define void @__masked_store_64(<4 x i64>* nocapture, <4 x i64>, <4 x i32>) nounwind alwaysinline {
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per_lane(4, <4 x i32> %2, `
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%ptr_ID = getelementptr <4 x i64> * %0, i32 0, i32 LANE
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%storeval_ID = extractelement <4 x i64> %1, i32 LANE
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|
store i64 %storeval_ID, i64 * %ptr_ID')
|
|
ret void
|
|
}
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|
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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|
;; unaligned loads/loads+broadcasts
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|
|
|
load_and_broadcast(4, i32, 32)
|
|
load_and_broadcast(4, i64, 64)
|
|
load_masked(4, i32, 32, 4)
|
|
load_masked(4, i64, 64, 8)
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|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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|
;; gather/scatter
|
|
|
|
; define these with the macros from stdlib.m4
|
|
|
|
gen_gather(4, i32)
|
|
gen_gather(4, i64)
|
|
gen_scatter(4, i32)
|
|
gen_scatter(4, i64)
|