1d9201fe3d
When used, these targets end up with calls to undefined functions for all of the various special vector stuff ispc needs to compile ispc programs (masked store, gather, min/max, sqrt, etc.). These targets are not yet useful for anything, but are a step toward having an option to C++ code with calls out to intrinsics. Reorganized the directory structure a bit and put the LLVM bitcode used to define target-specific stuff (as well as some generic built-ins stuff) into a builtins/ directory. Note that for building on Windows, it's now necessary to set a LLVM_VERSION environment variable (with values like LLVM_2_9, LLVM_3_0, LLVM_3_1svn, etc.)
275 lines
10 KiB
LLVM
275 lines
10 KiB
LLVM
;; Copyright (c) 2010-2011, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ctlztz()
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define_prefetches()
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
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define float @__round_uniform_float(float) nounwind readonly alwaysinline {
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; roundss, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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; the roundss intrinsic is a total mess--docs say:
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;
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; __m128 _mm_round_ss (__m128 a, __m128 b, const int c)
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;
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; b is a 128-bit parameter. The lowest 32 bits are the result of the rounding function
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; on b0. The higher order 96 bits are copied directly from input parameter a. The
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; return value is described by the following equations:
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;
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; r0 = RND(b0)
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; r1 = a1
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; r2 = a2
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; r3 = a3
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;
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; It doesn't matter what we pass as a, since we only need the r0 value
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; here. So we pass the same register for both. Further, only the 0th
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; element of the b parameter matters
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%xi = insertelement <4 x float> undef, float %0, i32 0
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 8)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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define float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round down 0b01 | don't signal precision exceptions 0b1010 = 9
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 9)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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define float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 10)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
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define double @__round_uniform_double(double) nounwind readonly alwaysinline {
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%xi = insertelement <2 x double> undef, double %0, i32 0
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 8)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; do the rcpss call
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%vecval = insertelement <4 x float> undef, float %0, i32 0
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%call = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecval)
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%scall = extractelement <4 x float> %call, i32 0
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; do one N-R iteration to improve precision, as above
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%v_iv = fmul float %0, %scall
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%two_minus = fsub float 2., %v_iv
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%iv_mul = fmul float %scall, %two_minus
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ret float %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; rsqrt
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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define float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
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; uniform float is = extract(__rsqrt_u(v), 0);
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%v = insertelement <4 x float> undef, float %0, i32 0
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%vis = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %v)
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%is = extractelement <4 x float> %vis, i32 0
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul float %0, %is
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%v_is_is = fmul float %v_is, %is
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%three_sub = fsub float 3., %v_is_is
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%is_mul = fmul float %is, %three_sub
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%half_scale = fmul float 0.5, %is_mul
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ret float %half_scale
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; sqrt
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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define float @__sqrt_uniform_float(float) nounwind readonly alwaysinline {
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sse_unary_scalar(ret, 4, float, @llvm.x86.sse.sqrt.ss, %0)
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; fast math mode
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declare void @llvm.x86.sse.stmxcsr(i8 *) nounwind
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declare void @llvm.x86.sse.ldmxcsr(i8 *) nounwind
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define void @__fastmath() nounwind alwaysinline {
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%ptr = alloca i32
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%ptr8 = bitcast i32 * %ptr to i8 *
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call void @llvm.x86.sse.stmxcsr(i8 * %ptr8)
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%oldval = load i32 *%ptr
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; turn on DAZ (64)/FTZ (32768) -> 32832
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%update = or i32 %oldval, 32832
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store i32 %update, i32 *%ptr
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call void @llvm.x86.sse.ldmxcsr(i8 * %ptr8)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
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define float @__max_uniform_float(float, float) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, float, @llvm.x86.sse.max.ss, %0, %1)
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ret float %ret
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}
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define float @__min_uniform_float(float, float) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, float, @llvm.x86.sse.min.ss, %0, %1)
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ret float %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define double @__sqrt_uniform_double(double) nounwind alwaysinline {
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sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
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define double @__min_uniform_double(double, double) nounwind readnone {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.min.sd, %0, %1)
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ret double %ret
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}
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define double @__max_uniform_double(double, double) nounwind readnone {
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sse_binary_scalar(ret, 2, double, @llvm.x86.sse2.max.sd, %0, %1)
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ret double %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 min/max
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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define i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pminsd, %0, %1)
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ret i32 %ret
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}
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define i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pmaxsd, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; unsigned int min/max
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declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
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define i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pminud, %0, %1)
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ret i32 %ret
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}
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define i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pmaxud, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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define i32 @__popcnt_int32(i32) nounwind readonly alwaysinline {
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%call = call i32 @llvm.ctpop.i32(i32 %0)
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ret i32 %call
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}
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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define i64 @__popcnt_int64(i64) nounwind readonly alwaysinline {
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%call = call i64 @llvm.ctpop.i64(i64 %0)
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ret i64 %call
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}
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