255 lines
10 KiB
LLVM
255 lines
10 KiB
LLVM
;; Copyright (c) 2011-2015, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;; This file defines various functions that are used when generating the
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;; the "dispatch" object/assembly file that has entrypoints for each
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;; exported function in a module that dispatch to the best available
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;; variant of that function that will run on the system's CPU.
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;; Stores the best target ISA that the system on which we're actually
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;; running supports. -1 represents "uninitialized", otherwise this value
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;; should correspond to one of the enumerant values of Target::ISA from
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;; ispc.h.
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@__system_best_isa = internal global i32 -1
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;; The below is the result of running "clang -O2 -emit-llvm -c -o -" on the
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;; following code... Specifically, __get_system_isa should return a value
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;; corresponding to one of the Target::ISA enumerant values that gives the
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;; most capable ISA that the curremt system can run.
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;;
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;;
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;; #include <stdint.h>
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;; #include <stdlib.h>
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;;
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;; static void __cpuid(int info[4], int infoType) {
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;; __asm__ __volatile__ ("cpuid"
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;; : "=a" (info[0]), "=b" (info[1]), "=c" (info[2]), "=d" (info[3])
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;; : "0" (infoType));
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;; }
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;;
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;; // Save %ebx in case it's the PIC register.
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;; static void __cpuid_count(int info[4], int level, int count) {
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;; __asm__ __volatile__ ("xchg{l}\t{%%}ebx, %1\n\t"
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;; "cpuid\n\t"
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;; "xchg{l}\t{%%}ebx, %1\n\t"
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;; : "=a" (info[0]), "=r" (info[1]), "=c" (info[2]), "=d" (info[3])
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;; : "0" (level), "2" (count));
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;; }
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;;
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;; static int __os_has_avx_support() {
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;; // Check xgetbv; this uses a .byte sequence instead of the instruction
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;; // directly because older assemblers do not include support for xgetbv and
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;; // there is no easy way to conditionally compile based on the assembler used.
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;; int rEAX, rEDX;
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;; __asm__ __volatile__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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;; return (rEAX & 6) == 6;
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;; }
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;;
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;; static int __os_has_avx512_support() {
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;; // Check if the OS saves the XMM, YMM and ZMM registers, i.e. it supports AVX2 and AVX512.
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;; // See section 2.1 of software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
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;; // Check xgetbv; this uses a .byte sequence instead of the instruction
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;; // directly because older assemblers do not include support for xgetbv and
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;; // there is no easy way to conditionally compile based on the assembler used.
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;; int rEAX, rEDX;
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;; __asm__ __volatile__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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;; return (rEAX & 0xE6) == 0xE6;
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;; }
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;;
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;; int32_t __get_system_isa() {
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;; int info[4];
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;; __cpuid(info, 1);
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;;
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;; // Call cpuid with eax=7, ecx=0
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;; int info2[4];
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;; __cpuid_count(info2, 7, 0);
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;;
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;; // NOTE: the values returned below must be the same as the
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;; // corresponding enumerant values in Target::ISA.
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;; if ((info[2] & (1 << 27)) != 0 && // OSXSAVE
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;; (info2[1] & (1 << 5)) != 0 && // AVX2
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;; (info2[1] & (1 << 16)) != 0 && // AVX512 F
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;; __os_has_avx512_support()) {
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;; // We need to verify that AVX2 is also available,
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;; // as well as AVX512, because our targets are supposed
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;; // to use both.
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;;
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;; if ((info2[1] & (1 << 17)) != 0 && // AVX512 DQ
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;; (info2[1] & (1 << 28)) != 0 && // AVX512 CDI
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;; (info2[1] & (1 << 30)) != 0 && // AVX512 BW
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;; (info2[1] & (1 << 31)) != 0) { // AVX512 VL
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;; return 6; // SKX
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;; }
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;; else if ((info2[1] & (1 << 26)) != 0 && // AVX512 PF
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;; (info2[1] & (1 << 27)) != 0 && // AVX512 ER
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;; (info2[1] & (1 << 28)) != 0) { // AVX512 CDI
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;; return 5; // KNL_AVX512
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;; }
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;; // If it's unknown AVX512 target, fall through and use AVX2
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;; // or whatever is available in the machine.
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;; }
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;;
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;; if ((info[2] & (1 << 27)) != 0 && // OSXSAVE
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;; (info[2] & (1 << 28)) != 0 &&
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;; __os_has_avx_support()) {
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;; if ((info[2] & (1 << 29)) != 0 && // F16C
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;; (info[2] & (1 << 30)) != 0) { // RDRAND
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;; // So far, so good. AVX2?
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;; if ((info2[1] & (1 << 5)) != 0)
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;; return 4;
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;; else
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;; return 3;
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;; }
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;; // Regular AVX
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;; return 2;
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;; }
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;; else if ((info[2] & (1 << 19)) != 0)
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;; return 1; // SSE4
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;; else if ((info[3] & (1 << 26)) != 0)
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;; return 0; // SSE2
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;; else
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;; abort();
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;; }
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; LLVM has different IR for different versions since 3.7
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define(`PTR_OP_ARGS',
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ifelse(LLVM_VERSION, LLVM_3_7,
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``$1 , $1 *'',
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LLVM_VERSION, LLVM_3_8,
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``$1 , $1 *'',
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``$1 *''
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)
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)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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define i32 @__get_system_isa() nounwind uwtable {
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entry:
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%0 = tail call { i32, i32, i32, i32 } asm sideeffect "cpuid", "={ax},={bx},={cx},={dx},0,~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
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%asmresult5.i = extractvalue { i32, i32, i32, i32 } %0, 2
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%asmresult6.i = extractvalue { i32, i32, i32, i32 } %0, 3
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%1 = tail call { i32, i32, i32, i32 } asm sideeffect "xchg$(l$)\09$(%$)ebx, $1\0A\09cpuid\0A\09xchg$(l$)\09$(%$)ebx, $1\0A\09", "={ax},=r,={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}"(i32 7, i32 0) nounwind
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%asmresult4.i87 = extractvalue { i32, i32, i32, i32 } %1, 1
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%and = and i32 %asmresult5.i, 134217728
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%cmp = icmp eq i32 %and, 0
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br i1 %cmp, label %if.else65, label %land.lhs.true
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land.lhs.true: ; preds = %entry
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%2 = and i32 %asmresult4.i87, 65568
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%3 = icmp eq i32 %2, 65568
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br i1 %3, label %land.lhs.true9, label %if.end39
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land.lhs.true9: ; preds = %land.lhs.true
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%4 = tail call { i32, i32 } asm sideeffect ".byte 0x0f, 0x01, 0xd0", "={ax},={dx},{cx},~{dirflag},~{fpsr},~{flags}"(i32 0) nounwind
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%asmresult.i90 = extractvalue { i32, i32 } %4, 0
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%and.i = and i32 %asmresult.i90, 230
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%cmp.i = icmp eq i32 %and.i, 230
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br i1 %cmp.i, label %if.then, label %if.end39
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if.then: ; preds = %land.lhs.true9
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%5 = and i32 %asmresult4.i87, -805175296
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%6 = icmp eq i32 %5, -805175296
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br i1 %6, label %return, label %if.else
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if.else: ; preds = %if.then
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%7 = and i32 %asmresult4.i87, 469762048
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%8 = icmp eq i32 %7, 469762048
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br i1 %8, label %return, label %if.end39
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if.end39: ; preds = %if.else, %land.lhs.true9, %land.lhs.true
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%9 = and i32 %asmresult5.i, 402653184
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%10 = icmp eq i32 %9, 402653184
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br i1 %10, label %land.lhs.true47, label %if.else65
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land.lhs.true47: ; preds = %if.end39
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%11 = tail call { i32, i32 } asm sideeffect ".byte 0x0f, 0x01, 0xd0", "={ax},={dx},{cx},~{dirflag},~{fpsr},~{flags}"(i32 0) nounwind
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%asmresult.i91 = extractvalue { i32, i32 } %11, 0
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%and.i92 = and i32 %asmresult.i91, 6
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%cmp.i93 = icmp eq i32 %and.i92, 6
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br i1 %cmp.i93, label %if.then50, label %if.else65
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if.then50: ; preds = %land.lhs.true47
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%12 = and i32 %asmresult5.i, 1610612736
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%13 = icmp eq i32 %12, 1610612736
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br i1 %13, label %if.then58, label %return
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if.then58: ; preds = %if.then50
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%and60 = lshr i32 %asmresult4.i87, 5
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%14 = and i32 %and60, 1
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%15 = add i32 %14, 3
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br label %return
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if.else65: ; preds = %land.lhs.true47, %if.end39, %entry
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%and67 = and i32 %asmresult5.i, 524288
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%cmp68 = icmp eq i32 %and67, 0
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br i1 %cmp68, label %if.else70, label %return
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if.else70: ; preds = %if.else65
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%and72 = and i32 %asmresult6.i, 67108864
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%cmp73 = icmp eq i32 %and72, 0
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br i1 %cmp73, label %if.else75, label %return
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if.else75: ; preds = %if.else70
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tail call void @abort() noreturn nounwind
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unreachable
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return: ; preds = %if.else70, %if.else65, %if.then58, %if.then50, %if.else, %if.then
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%retval.0 = phi i32 [ 6, %if.then ], [ 5, %if.else ], [ %15, %if.then58 ], [ 2, %if.then50 ], [ 1, %if.else65 ], [ 0, %if.else70 ]
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ret i32 %retval.0
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}
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declare void @abort() noreturn nounwind
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; This function is called by each of the dispatch functions we generate;
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;; it sets @__system_best_isa if it is unset.
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define void @__set_system_isa() {
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entry:
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%bi = load PTR_OP_ARGS(`i32 ') @__system_best_isa
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%unset = icmp eq i32 %bi, -1
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br i1 %unset, label %set_system_isa, label %done
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set_system_isa:
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%bival = call i32 @__get_system_isa()
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store i32 %bival, i32* @__system_best_isa
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ret void
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done:
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ret void
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}
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