79 lines
3.4 KiB
Diff
79 lines
3.4 KiB
Diff
From b9c47f44691cb9a648b9fa1ae373f0defe53c757 Mon Sep 17 00:00:00 2001
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From: Michael Liao <michael.hliao@gmail.com>
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Date: Thu, 10 Oct 2013 16:47:00 -0700
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Subject: [PATCH] Fix PR16807
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- Lower signed division by constant powers-of-2 to target-independent
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DAG operators instead of target-dependent ones to support them on
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targets where vector types are legal but shift operators on that types
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are illegal, e.g. on AVX, PSRAW is only available on <8 x i16> though
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<16 x i16> is a legal type.
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---
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lib/Target/X86/X86ISelLowering.cpp | 22 ++++++++++++++++------
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test/CodeGen/X86/pr16807.ll | 18 ++++++++++++++++++
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2 files changed, 34 insertions(+), 6 deletions(-)
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create mode 100644 test/CodeGen/X86/pr16807.ll
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diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
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index bd5ad4e..518bb90 100644
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--- lib/Target/X86/X86ISelLowering.cpp
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+++ lib/Target/X86/X86ISelLowering.cpp
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@@ -12462,14 +12462,24 @@ static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
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(SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
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unsigned lg2 = SplatValue.countTrailingZeros();
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// Splat the sign bit.
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- SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
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- SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
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+ SmallVector<SDValue, 16> Sz(NumElts,
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+ DAG.getConstant(EltTy.getSizeInBits() - 1,
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+ EltTy));
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+ SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
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+ DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
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+ NumElts));
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// Add (N0 < 0) ? abs2 - 1 : 0;
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- SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
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- SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
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+ SmallVector<SDValue, 16> Amt(NumElts,
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+ DAG.getConstant(EltTy.getSizeInBits() - lg2,
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+ EltTy));
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+ SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
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+ DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
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+ NumElts));
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SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
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- SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
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- SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
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+ SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(lg2, EltTy));
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+ SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
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+ DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
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+ NumElts));
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// If we're dividing by a positive value, we're done. Otherwise, we must
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// negate the result.
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diff --git a/test/CodeGen/X86/pr16807.ll b/test/CodeGen/X86/pr16807.ll
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new file mode 100644
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index 0000000..6d55d99
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--- /dev/null
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+++ test/CodeGen/X86/pr16807.ll
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@@ -0,0 +1,18 @@
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+; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core-avx-i | FileCheck %s
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+
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+define <16 x i16> @f_fu(<16 x i16> %bf) {
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+allocas:
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+ %avg.i.i = sdiv <16 x i16> %bf, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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+ ret <16 x i16> %avg.i.i
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+}
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+
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+; CHECK: f_fu
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+; CHECK: psraw
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+; CHECK: psrlw
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+; CHECK: paddw
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+; CHECK: psraw
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+; CHECK: psraw
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+; CHECK: psrlw
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+; CHECK: paddw
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+; CHECK: psraw
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+; CHECK: ret
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--
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1.8.1.2
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