355 lines
12 KiB
LLVM
355 lines
12 KiB
LLVM
;;
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;; target-neon-common.ll
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;;
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;; Copyright(c) 2013-2015 Google, Inc.
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;;
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Matt Pharr nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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target datalayout = "e-p:32:32:32-S32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f16:16:16-f32:32:32-f64:32:64-f128:128:128-v64:32:64-v128:32:128-a0:0:64-n32"
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stdlib_core()
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scans()
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reduce_equal(WIDTH)
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rdrand_decls()
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define_shuffles()
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aossoa()
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ctlztz()
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
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define float @__half_to_float_uniform(i16 %v) nounwind readnone alwaysinline {
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%v1 = bitcast i16 %v to <1 x i16>
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%vec = shufflevector <1 x i16> %v1, <1 x i16> undef,
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<4 x i32> <i32 0, i32 0, i32 0, i32 0>
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%h = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %vec)
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%r = extractelement <4 x float> %h, i32 0
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ret float %r
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}
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define i16 @__float_to_half_uniform(float %v) nounwind readnone alwaysinline {
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%v1 = bitcast float %v to <1 x float>
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%vec = shufflevector <1 x float> %v1, <1 x float> undef,
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<4 x i32> <i32 0, i32 0, i32 0, i32 0>
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%h = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %vec)
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%r = extractelement <4 x i16> %h, i32 0
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ret i16 %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; math
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declare i32 @llvm.arm.get.fpscr() nounwind
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declare void @llvm.arm.set.fpscr(i32) nounwind
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define void @__fastmath() nounwind alwaysinline {
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%x = call i32 @llvm.arm.get.fpscr()
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; Turn on FTZ (bit 24) and default NaN (bit 25)
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%y = or i32 %x, 50331648
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call void @llvm.arm.set.fpscr(i32 %y)
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ret void
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}
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;; round/floor/ceil
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;; FIXME: grabbed these from the sse2 target, which does not have native
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;; instructions for these. Is there a better approach for NEON?
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define float @__round_uniform_float(float) nounwind readonly alwaysinline {
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%float_to_int_bitcast.i.i.i.i = bitcast float %0 to i32
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%bitop.i.i = and i32 %float_to_int_bitcast.i.i.i.i, -2147483648
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%bitop.i = xor i32 %bitop.i.i, %float_to_int_bitcast.i.i.i.i
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%int_to_float_bitcast.i.i40.i = bitcast i32 %bitop.i to float
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%binop.i = fadd float %int_to_float_bitcast.i.i40.i, 8.388608e+06
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%binop21.i = fadd float %binop.i, -8.388608e+06
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%float_to_int_bitcast.i.i.i = bitcast float %binop21.i to i32
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%bitop31.i = xor i32 %float_to_int_bitcast.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i.i = bitcast i32 %bitop31.i to float
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ret float %int_to_float_bitcast.i.i.i
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}
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define float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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%calltmp.i = tail call float @__round_uniform_float(float %0) nounwind
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%bincmp.i = fcmp ogt float %calltmp.i, %0
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%selectexpr.i = sext i1 %bincmp.i to i32
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%bitop.i = and i32 %selectexpr.i, -1082130432
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%int_to_float_bitcast.i.i.i = bitcast i32 %bitop.i to float
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%binop.i = fadd float %calltmp.i, %int_to_float_bitcast.i.i.i
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ret float %binop.i
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}
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define float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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%calltmp.i = tail call float @__round_uniform_float(float %0) nounwind
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%bincmp.i = fcmp olt float %calltmp.i, %0
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%selectexpr.i = sext i1 %bincmp.i to i32
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%bitop.i = and i32 %selectexpr.i, 1065353216
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%int_to_float_bitcast.i.i.i = bitcast i32 %bitop.i to float
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%binop.i = fadd float %calltmp.i, %int_to_float_bitcast.i.i.i
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ret float %binop.i
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}
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;; FIXME: rounding doubles and double vectors needs to be implemented
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declare double @__round_uniform_double(double) nounwind readnone
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declare double @__floor_uniform_double(double) nounwind readnone
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declare double @__ceil_uniform_double(double) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; min/max
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define float @__max_uniform_float(float, float) nounwind readnone alwaysinline {
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%cmp = fcmp ugt float %0, %1
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%r = select i1 %cmp, float %0, float %1
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ret float %r
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}
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define float @__min_uniform_float(float, float) nounwind readnone alwaysinline {
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%cmp = fcmp ult float %0, %1
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%r = select i1 %cmp, float %0, float %1
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ret float %r
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}
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define i32 @__min_uniform_int32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp slt i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__max_uniform_int32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp sgt i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__min_uniform_uint32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp ult i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__max_uniform_uint32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp ugt i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i64 @__min_uniform_int64(i64, i64) nounwind readnone alwaysinline {
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%cmp = icmp slt i64 %0, %1
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%r = select i1 %cmp, i64 %0, i64 %1
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ret i64 %r
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}
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define i64 @__max_uniform_int64(i64, i64) nounwind readnone alwaysinline {
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%cmp = icmp sgt i64 %0, %1
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%r = select i1 %cmp, i64 %0, i64 %1
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ret i64 %r
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}
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define i64 @__min_uniform_uint64(i64, i64) nounwind readnone alwaysinline {
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%cmp = icmp ult i64 %0, %1
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%r = select i1 %cmp, i64 %0, i64 %1
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ret i64 %r
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}
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define i64 @__max_uniform_uint64(i64, i64) nounwind readnone alwaysinline {
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%cmp = icmp ugt i64 %0, %1
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%r = select i1 %cmp, i64 %0, i64 %1
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ret i64 %r
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}
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define double @__min_uniform_double(double, double) nounwind readnone alwaysinline {
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%cmp = fcmp olt double %0, %1
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%r = select i1 %cmp, double %0, double %1
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ret double %r
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}
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define double @__max_uniform_double(double, double) nounwind readnone alwaysinline {
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%cmp = fcmp ogt double %0, %1
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%r = select i1 %cmp, double %0, double %1
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ret double %r
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}
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define <WIDTH x i64> @__min_varying_int64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone alwaysinline {
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%m = icmp slt <WIDTH x i64> %0, %1
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%r = select <WIDTH x i1> %m, <WIDTH x i64> %0, <WIDTH x i64> %1
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ret <WIDTH x i64> %r
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}
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define <WIDTH x i64> @__max_varying_int64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone alwaysinline {
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%m = icmp sgt <WIDTH x i64> %0, %1
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%r = select <WIDTH x i1> %m, <WIDTH x i64> %0, <WIDTH x i64> %1
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ret <WIDTH x i64> %r
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}
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define <WIDTH x i64> @__min_varying_uint64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone alwaysinline {
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%m = icmp ult <WIDTH x i64> %0, %1
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%r = select <WIDTH x i1> %m, <WIDTH x i64> %0, <WIDTH x i64> %1
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ret <WIDTH x i64> %r
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}
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define <WIDTH x i64> @__max_varying_uint64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone alwaysinline {
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%m = icmp ugt <WIDTH x i64> %0, %1
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%r = select <WIDTH x i1> %m, <WIDTH x i64> %0, <WIDTH x i64> %1
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ret <WIDTH x i64> %r
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}
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define <WIDTH x double> @__min_varying_double(<WIDTH x double>,
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<WIDTH x double>) nounwind readnone alwaysinline {
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%m = fcmp olt <WIDTH x double> %0, %1
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%r = select <WIDTH x i1> %m, <WIDTH x double> %0, <WIDTH x double> %1
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ret <WIDTH x double> %r
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}
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define <WIDTH x double> @__max_varying_double(<WIDTH x double>,
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<WIDTH x double>) nounwind readnone alwaysinline {
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%m = fcmp ogt <WIDTH x double> %0, %1
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%r = select <WIDTH x i1> %m, <WIDTH x double> %0, <WIDTH x double> %1
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ret <WIDTH x double> %r
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}
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;; sqrt/rsqrt/rcp
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declare float @llvm.sqrt.f32(float)
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define float @__sqrt_uniform_float(float) nounwind readnone alwaysinline {
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%r = call float @llvm.sqrt.f32(float %0)
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ret float %r
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}
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declare double @llvm.sqrt.f64(double)
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define double @__sqrt_uniform_double(double) nounwind readnone alwaysinline {
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%r = call double @llvm.sqrt.f64(double %0)
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ret double %r
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}
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;; bit ops
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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define i32 @__popcnt_int32(i32) nounwind readnone alwaysinline {
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%v = call i32 @llvm.ctpop.i32(i32 %0)
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ret i32 %v
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}
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define i64 @__popcnt_int64(i64) nounwind readnone alwaysinline {
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%v = call i64 @llvm.ctpop.i64(i64 %0)
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ret i64 %v
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unaligned loads/loads+broadcasts
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masked_load(i8, 1)
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masked_load(i16, 2)
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masked_load(i32, 4)
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masked_load(float, 4)
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masked_load(i64, 8)
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masked_load(double, 8)
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gen_masked_store(i8)
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gen_masked_store(i16)
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gen_masked_store(i32)
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gen_masked_store(i64)
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masked_store_float_double()
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define void @__masked_store_blend_i8(<WIDTH x i8>* nocapture %ptr, <WIDTH x i8> %new,
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<WIDTH x MASK> %mask) nounwind alwaysinline {
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%old = load PTR_OP_ARGS(`<WIDTH x i8> ') %ptr
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%mask1 = trunc <WIDTH x MASK> %mask to <WIDTH x i1>
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%result = select <WIDTH x i1> %mask1, <WIDTH x i8> %new, <WIDTH x i8> %old
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store <WIDTH x i8> %result, <WIDTH x i8> * %ptr
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ret void
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}
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define void @__masked_store_blend_i16(<WIDTH x i16>* nocapture %ptr, <WIDTH x i16> %new,
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<WIDTH x MASK> %mask) nounwind alwaysinline {
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%old = load PTR_OP_ARGS(`<WIDTH x i16> ') %ptr
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%mask1 = trunc <WIDTH x MASK> %mask to <WIDTH x i1>
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%result = select <WIDTH x i1> %mask1, <WIDTH x i16> %new, <WIDTH x i16> %old
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store <WIDTH x i16> %result, <WIDTH x i16> * %ptr
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ret void
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}
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define void @__masked_store_blend_i32(<WIDTH x i32>* nocapture %ptr, <WIDTH x i32> %new,
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<WIDTH x MASK> %mask) nounwind alwaysinline {
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%old = load PTR_OP_ARGS(`<WIDTH x i32> ') %ptr
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%mask1 = trunc <WIDTH x MASK> %mask to <WIDTH x i1>
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%result = select <WIDTH x i1> %mask1, <WIDTH x i32> %new, <WIDTH x i32> %old
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store <WIDTH x i32> %result, <WIDTH x i32> * %ptr
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ret void
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}
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define void @__masked_store_blend_i64(<WIDTH x i64>* nocapture %ptr,
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<WIDTH x i64> %new, <WIDTH x MASK> %mask) nounwind alwaysinline {
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%old = load PTR_OP_ARGS(`<WIDTH x i64> ') %ptr
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%mask1 = trunc <WIDTH x MASK> %mask to <WIDTH x i1>
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%result = select <WIDTH x i1> %mask1, <WIDTH x i64> %new, <WIDTH x i64> %old
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store <WIDTH x i64> %result, <WIDTH x i64> * %ptr
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ret void
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}
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;; yuck. We need declarations of these, even though we shouldnt ever
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;; actually generate calls to them for the NEON target...
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include(`svml.m4')
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svml_stubs(float,f,WIDTH)
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svml_stubs(double,d,WIDTH)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; gather
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gen_gather_factored(i8)
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gen_gather_factored(i16)
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gen_gather_factored(i32)
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gen_gather_factored(float)
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gen_gather_factored(i64)
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gen_gather_factored(double)
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gen_scatter(i8)
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gen_scatter(i16)
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gen_scatter(i32)
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gen_scatter(float)
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gen_scatter(i64)
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gen_scatter(double)
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packed_load_and_store(4)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; prefetch
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define_prefetches()
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declare_nvptx()
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