594 lines
24 KiB
LLVM
594 lines
24 KiB
LLVM
;;
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;; target-neon-8.ll
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;;
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;; Copyright(c) 2013-2015 Google, Inc.
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;;
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Matt Pharr nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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define(`WIDTH',`16')
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define(`MASK',`i8')
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include(`util.m4')
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include(`target-neon-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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define <16 x float> @__half_to_float_varying(<16 x i16> %v) nounwind readnone alwaysinline {
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unary4to16conv(r, i16, float, @llvm.arm.neon.vcvthf2fp, %v)
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ret <16 x float> %r
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}
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define <16 x i16> @__float_to_half_varying(<16 x float> %v) nounwind readnone alwaysinline {
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unary4to16conv(r, float, i16, @llvm.arm.neon.vcvtfp2hf, %v)
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ret <16 x i16> %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; math
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;; round/floor/ceil
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;; FIXME: grabbed these from the sse2 target, which does not have native
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;; instructions for these. Is there a better approach for NEON?
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define <16 x float> @__round_varying_float(<16 x float>) nounwind readonly alwaysinline {
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%float_to_int_bitcast.i.i.i.i = bitcast <16 x float> %0 to <16 x i32>
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%bitop.i.i = and <16 x i32> %float_to_int_bitcast.i.i.i.i,
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<i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648,
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i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648,
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i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648,
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i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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%bitop.i = xor <16 x i32> %float_to_int_bitcast.i.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i40.i = bitcast <16 x i32> %bitop.i to <16 x float>
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%binop.i = fadd <16 x float> %int_to_float_bitcast.i.i40.i,
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<float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06,
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float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06,
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float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06,
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float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>
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%binop21.i = fadd <16 x float> %binop.i,
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<float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06,
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float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06,
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float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06,
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float -8.388608e+06, float -8.388608e+06, float -8.388608e+06, float -8.388608e+06>
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%float_to_int_bitcast.i.i.i = bitcast <16 x float> %binop21.i to <16 x i32>
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%bitop31.i = xor <16 x i32> %float_to_int_bitcast.i.i.i, %bitop.i.i
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%int_to_float_bitcast.i.i.i = bitcast <16 x i32> %bitop31.i to <16 x float>
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ret <16 x float> %int_to_float_bitcast.i.i.i
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}
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define <16 x float> @__floor_varying_float(<16 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <16 x float> @__round_varying_float(<16 x float> %0) nounwind
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%bincmp.i = fcmp ogt <16 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <16 x i1> %bincmp.i to <16 x i32>
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%bitop.i = and <16 x i32> %val_to_boolvec32.i,
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<i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432,
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i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432,
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i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432,
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i32 -1082130432, i32 -1082130432, i32 -1082130432, i32 -1082130432>
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%int_to_float_bitcast.i.i.i = bitcast <16 x i32> %bitop.i to <16 x float>
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%binop.i = fadd <16 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <16 x float> %binop.i
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}
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define <16 x float> @__ceil_varying_float(<16 x float>) nounwind readonly alwaysinline {
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%calltmp.i = tail call <16 x float> @__round_varying_float(<16 x float> %0) nounwind
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%bincmp.i = fcmp olt <16 x float> %calltmp.i, %0
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%val_to_boolvec32.i = sext <16 x i1> %bincmp.i to <16 x i32>
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%bitop.i = and <16 x i32> %val_to_boolvec32.i,
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<i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216,
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i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216,
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i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216,
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i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
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%int_to_float_bitcast.i.i.i = bitcast <16 x i32> %bitop.i to <16 x float>
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%binop.i = fadd <16 x float> %calltmp.i, %int_to_float_bitcast.i.i.i
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ret <16 x float> %binop.i
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}
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;; FIXME: rounding doubles and double vectors needs to be implemented
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declare <WIDTH x double> @__round_varying_double(<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__floor_varying_double(<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__ceil_varying_double(<WIDTH x double>) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; min/max
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declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__max_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone alwaysinline {
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binary4to16(r, float, @llvm.arm.neon.vmaxs.v4f32, %0, %1)
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ret <WIDTH x float> %r
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}
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define <WIDTH x float> @__min_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone alwaysinline {
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binary4to16(r, float, @llvm.arm.neon.vmins.v4f32, %0, %1)
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ret <WIDTH x float> %r
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}
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declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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define <WIDTH x i32> @__min_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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binary4to16(r, i32, @llvm.arm.neon.vmins.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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define <WIDTH x i32> @__max_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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binary4to16(r, i32, @llvm.arm.neon.vmaxs.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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define <WIDTH x i32> @__min_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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binary4to16(r, i32, @llvm.arm.neon.vminu.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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define <WIDTH x i32> @__max_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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binary4to16(r, i32, @llvm.arm.neon.vmaxu.v4i32, %0, %1)
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ret <WIDTH x i32> %r
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}
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;; sqrt/rsqrt/rcp
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__rcp_varying_float(<WIDTH x float> %d) nounwind readnone alwaysinline {
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unary4to16(x0, float, @llvm.arm.neon.vrecpe.v4f32, %d)
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binary4to16(x0_nr, float, @llvm.arm.neon.vrecps.v4f32, %d, %x0)
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%x1 = fmul <WIDTH x float> %x0, %x0_nr
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binary4to16(x1_nr, float, @llvm.arm.neon.vrecps.v4f32, %d, %x1)
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%x2 = fmul <WIDTH x float> %x1, %x1_nr
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ret <WIDTH x float> %x2
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}
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declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %d) nounwind readnone alwaysinline {
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unary4to16(x0, float, @llvm.arm.neon.vrsqrte.v4f32, %d)
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%x0_2 = fmul <WIDTH x float> %x0, %x0
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binary4to16(x0_nr, float, @llvm.arm.neon.vrsqrts.v4f32, %d, %x0_2)
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%x1 = fmul <WIDTH x float> %x0, %x0_nr
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%x1_2 = fmul <WIDTH x float> %x1, %x1
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binary4to16(x1_nr, float, @llvm.arm.neon.vrsqrts.v4f32, %d, %x1_2)
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%x2 = fmul <WIDTH x float> %x1, %x1_nr
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ret <WIDTH x float> %x2
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}
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define float @__rsqrt_uniform_float(float) nounwind readnone alwaysinline {
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%v1 = bitcast float %0 to <1 x float>
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%vs = shufflevector <1 x float> %v1, <1 x float> undef,
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<16 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%vr = call <16 x float> @__rsqrt_varying_float(<16 x float> %vs)
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%r = extractelement <16 x float> %vr, i32 0
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ret float %r
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}
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define float @__rcp_uniform_float(float) nounwind readnone alwaysinline {
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%v1 = bitcast float %0 to <1 x float>
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%vs = shufflevector <1 x float> %v1, <1 x float> undef,
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<16 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%vr = call <16 x float> @__rcp_varying_float(<16 x float> %vs)
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%r = extractelement <16 x float> %vr, i32 0
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ret float %r
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}
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
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define <WIDTH x float> @__sqrt_varying_float(<WIDTH x float>) nounwind readnone alwaysinline {
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unary4to16(result, float, @llvm.sqrt.v4f32, %0)
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;; this returns nan for v=0, which is undesirable..
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;; %rsqrt = call <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %0)
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;; %result = fmul <4 x float> %rsqrt, %0
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ret <16 x float> %result
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}
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declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
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define <WIDTH x double> @__sqrt_varying_double(<WIDTH x double>) nounwind readnone alwaysinline {
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unary4to16(r, double, @llvm.sqrt.v4f64, %0)
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ret <WIDTH x double> %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; reductions
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define i64 @__movmsk(<WIDTH x MASK>) nounwind readnone alwaysinline {
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%and_mask = and <WIDTH x i8> %0,
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<i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 128,
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i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 128>
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%v8 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %and_mask)
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%v4 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %v8)
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%v2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %v4)
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%va = extractelement <2 x i64> %v2, i32 0
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%vb = extractelement <2 x i64> %v2, i32 1
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%vbshift = shl i64 %vb, 8
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%v = or i64 %va, %vbshift
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ret i64 %v
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}
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define i1 @__any(<WIDTH x MASK>) nounwind readnone alwaysinline {
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v16tov8(MASK, %0, %v8a, %v8b)
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%vor8 = or <8 x MASK> %v8a, %v8b
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%v16 = sext <8 x i8> %vor8 to <8 x i16>
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v8tov4(i16, %v16, %v16a, %v16b)
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%vor16 = or <4 x i16> %v16a, %v16b
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%v32 = sext <4 x i16> %vor16 to <4 x i32>
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v4tov2(i32, %v32, %v32a, %v32b)
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%vor32 = or <2 x i32> %v32a, %v32b
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%v0 = extractelement <2 x i32> %vor32, i32 0
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%v1 = extractelement <2 x i32> %vor32, i32 1
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%v = or i32 %v0, %v1
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%cmp = icmp ne i32 %v, 0
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ret i1 %cmp
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}
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define i1 @__all(<WIDTH x MASK>) nounwind readnone alwaysinline {
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v16tov8(MASK, %0, %v8a, %v8b)
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%vand8 = and <8 x MASK> %v8a, %v8b
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%v16 = sext <8 x i8> %vand8 to <8 x i16>
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v8tov4(i16, %v16, %v16a, %v16b)
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%vand16 = and <4 x i16> %v16a, %v16b
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%v32 = sext <4 x i16> %vand16 to <4 x i32>
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v4tov2(i32, %v32, %v32a, %v32b)
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%vand32 = and <2 x i32> %v32a, %v32b
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%v0 = extractelement <2 x i32> %vand32, i32 0
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%v1 = extractelement <2 x i32> %vand32, i32 1
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%v = and i32 %v0, %v1
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%cmp = icmp ne i32 %v, 0
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ret i1 %cmp
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}
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define i1 @__none(<WIDTH x MASK>) nounwind readnone alwaysinline {
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%any = call i1 @__any(<WIDTH x MASK> %0)
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%none = icmp eq i1 %any, 0
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ret i1 %none
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}
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;; $1: scalar type
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;; $2: vector/vector reduce function (2 x <WIDTH x vec> -> <WIDTH x vec>)
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;; $3: pairwise vector reduce function (2 x <2 x vec> -> <2 x vec>)
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;; $4: scalar reduce function
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define(`neon_reduce', `
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v16tov8($1, %0, %va, %vb)
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%va_16 = shufflevector <8 x $1> %va, <8 x $1> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%vb_16 = shufflevector <8 x $1> %vb, <8 x $1> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v8 = call <16 x $1> $2(<16 x $1> %va_16, <16 x $1> %vb_16)
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%v8a = shufflevector <16 x $1> %v8, <16 x $1> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v8b = shufflevector <16 x $1> %v8, <16 x $1> undef,
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<16 x i32> <i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v4 = call <16 x $1> $2(<16 x $1> %v8a, <16 x $1> %v8b)
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%vfirst_4 = shufflevector <16 x $1> %v4, <16 x $1> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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v4tov2($1, %vfirst_4, %v0, %v1)
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%vh = call <2 x $1> $3(<2 x $1> %v0, <2 x $1> %v1)
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%vh0 = extractelement <2 x $1> %vh, i32 0
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%vh1 = extractelement <2 x $1> %vh, i32 1
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%r = call $1 $4($1 %vh0, $1 %vh1)
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ret $1 %r
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')
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declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
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|
|
|
define internal float @add_f32(float, float) nounwind readnone alwaysinline {
|
|
%r = fadd float %0, %1
|
|
ret float %r
|
|
}
|
|
|
|
define internal <WIDTH x float> @__add_varying_float(<WIDTH x float>, <WIDTH x float>) nounwind readnone alwaysinline {
|
|
%r = fadd <WIDTH x float> %0, %1
|
|
ret <WIDTH x float> %r
|
|
}
|
|
|
|
define float @__reduce_add_float(<WIDTH x float>) nounwind readnone alwaysinline {
|
|
neon_reduce(float, @__add_varying_float, @llvm.arm.neon.vpadd.v2f32, @add_f32)
|
|
}
|
|
|
|
declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
|
|
|
define internal float @min_f32(float, float) nounwind readnone alwaysinline {
|
|
%cmp = fcmp olt float %0, %1
|
|
%r = select i1 %cmp, float %0, float %1
|
|
ret float %r
|
|
}
|
|
|
|
define float @__reduce_min_float(<WIDTH x float>) nounwind readnone alwaysinline {
|
|
neon_reduce(float, @__min_varying_float, @llvm.arm.neon.vpmins.v2f32, @min_f32)
|
|
}
|
|
|
|
declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
|
|
|
|
define internal float @max_f32(float, float) nounwind readnone alwaysinline {
|
|
%cmp = fcmp ugt float %0, %1
|
|
%r = select i1 %cmp, float %0, float %1
|
|
ret float %r
|
|
}
|
|
|
|
define float @__reduce_max_float(<WIDTH x float>) nounwind readnone alwaysinline {
|
|
neon_reduce(float, @__max_varying_float, @llvm.arm.neon.vpmaxs.v2f32, @max_f32)
|
|
}
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone
|
|
declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
|
|
declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
|
|
|
|
define i64 @__reduce_add_int8(<WIDTH x i8>) nounwind readnone alwaysinline {
|
|
%a16 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %0)
|
|
%a32 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %a16)
|
|
%a64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %a32)
|
|
%a0 = extractelement <2 x i64> %a64, i32 0
|
|
%a1 = extractelement <2 x i64> %a64, i32 1
|
|
%r = add i64 %a0, %a1
|
|
ret i64 %r
|
|
}
|
|
|
|
define i64 @__reduce_add_int16(<WIDTH x i16>) nounwind readnone alwaysinline {
|
|
v16tov8(i16, %0, %va, %vb)
|
|
%a32 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %va)
|
|
%b32 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %vb)
|
|
%a64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %a32)
|
|
%b64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %b32)
|
|
%sum = add <2 x i64> %a64, %b64
|
|
%a0 = extractelement <2 x i64> %sum, i32 0
|
|
%a1 = extractelement <2 x i64> %sum, i32 1
|
|
%r = add i64 %a0, %a1
|
|
ret i64 %r
|
|
}
|
|
|
|
define i64 @__reduce_add_int32(<WIDTH x i32>) nounwind readnone alwaysinline {
|
|
v16tov4(i32, %0, %va, %vb, %vc, %vd)
|
|
%a64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %va)
|
|
%b64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %vb)
|
|
%c64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %vc)
|
|
%d64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %vd)
|
|
%ab = add <2 x i64> %a64, %b64
|
|
%cd = add <2 x i64> %c64, %d64
|
|
%sum = add <2 x i64> %ab, %cd
|
|
%a0 = extractelement <2 x i64> %sum, i32 0
|
|
%a1 = extractelement <2 x i64> %sum, i32 1
|
|
%r = add i64 %a0, %a1
|
|
ret i64 %r
|
|
}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @min_si32(i32, i32) nounwind readnone alwaysinline {
|
|
%cmp = icmp slt i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_min_int32(<WIDTH x i32>) nounwind readnone alwaysinline {
|
|
neon_reduce(i32, @__min_varying_int32, @llvm.arm.neon.vpmins.v2i32, @min_si32)
|
|
}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @max_si32(i32, i32) nounwind readnone alwaysinline {
|
|
%cmp = icmp sgt i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_max_int32(<WIDTH x i32>) nounwind readnone alwaysinline {
|
|
neon_reduce(i32, @__max_varying_int32, @llvm.arm.neon.vpmaxs.v2i32, @max_si32)
|
|
}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @min_ui32(i32, i32) nounwind readnone alwaysinline {
|
|
%cmp = icmp ult i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_min_uint32(<WIDTH x i32>) nounwind readnone alwaysinline {
|
|
neon_reduce(i32, @__min_varying_uint32, @llvm.arm.neon.vpmins.v2i32, @min_ui32)
|
|
}
|
|
|
|
declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
|
|
define internal i32 @max_ui32(i32, i32) nounwind readnone alwaysinline {
|
|
%cmp = icmp ugt i32 %0, %1
|
|
%r = select i1 %cmp, i32 %0, i32 %1
|
|
ret i32 %r
|
|
}
|
|
|
|
define i32 @__reduce_max_uint32(<WIDTH x i32>) nounwind readnone alwaysinline {
|
|
neon_reduce(i32, @__max_varying_uint32, @llvm.arm.neon.vpmaxs.v2i32, @max_ui32)
|
|
}
|
|
|
|
define internal double @__add_uniform_double(double, double) nounwind readnone alwaysinline {
|
|
%r = fadd double %0, %1
|
|
ret double %r
|
|
}
|
|
|
|
define internal <WIDTH x double> @__add_varying_double(<WIDTH x double>, <WIDTH x double>) nounwind readnone alwaysinline {
|
|
%r = fadd <WIDTH x double> %0, %1
|
|
ret <WIDTH x double> %r
|
|
}
|
|
|
|
define double @__reduce_add_double(<WIDTH x double>) nounwind readnone alwaysinline {
|
|
reduce16(double, @__add_varying_double, @__add_uniform_double)
|
|
}
|
|
|
|
define double @__reduce_min_double(<WIDTH x double>) nounwind readnone alwaysinline {
|
|
reduce16(double, @__min_varying_double, @__min_uniform_double)
|
|
}
|
|
|
|
define double @__reduce_max_double(<WIDTH x double>) nounwind readnone alwaysinline {
|
|
reduce16(double, @__max_varying_double, @__max_uniform_double)
|
|
}
|
|
|
|
define internal i64 @__add_uniform_int64(i64, i64) nounwind readnone alwaysinline {
|
|
%r = add i64 %0, %1
|
|
ret i64 %r
|
|
}
|
|
|
|
define internal <WIDTH x i64> @__add_varying_int64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone alwaysinline {
|
|
%r = add <WIDTH x i64> %0, %1
|
|
ret <WIDTH x i64> %r
|
|
}
|
|
|
|
define i64 @__reduce_add_int64(<WIDTH x i64>) nounwind readnone alwaysinline {
|
|
reduce16(i64, @__add_varying_int64, @__add_uniform_int64)
|
|
}
|
|
|
|
define i64 @__reduce_min_int64(<WIDTH x i64>) nounwind readnone alwaysinline {
|
|
reduce16(i64, @__min_varying_int64, @__min_uniform_int64)
|
|
}
|
|
|
|
define i64 @__reduce_max_int64(<WIDTH x i64>) nounwind readnone alwaysinline {
|
|
reduce16(i64, @__max_varying_int64, @__max_uniform_int64)
|
|
}
|
|
|
|
define i64 @__reduce_min_uint64(<WIDTH x i64>) nounwind readnone alwaysinline {
|
|
reduce16(i64, @__min_varying_uint64, @__min_uniform_uint64)
|
|
}
|
|
|
|
define i64 @__reduce_max_uint64(<WIDTH x i64>) nounwind readnone alwaysinline {
|
|
reduce16(i64, @__max_varying_uint64, @__max_uniform_uint64)
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; int8/int16 builtins
|
|
|
|
declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
|
|
|
define <16 x i8> @__avg_up_uint8(<16 x i8>, <16 x i8>) nounwind readnone alwaysinline {
|
|
%r = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %0, <16 x i8> %1)
|
|
ret <16 x i8> %r
|
|
}
|
|
|
|
declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
|
|
|
define <16 x i8> @__avg_up_int8(<16 x i8>, <16 x i8>) nounwind readnone alwaysinline {
|
|
%r = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %0, <16 x i8> %1)
|
|
ret <16 x i8> %r
|
|
}
|
|
|
|
declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
|
|
|
define <16 x i8> @__avg_down_uint8(<16 x i8>, <16 x i8>) nounwind readnone alwaysinline {
|
|
%r = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %0, <16 x i8> %1)
|
|
ret <16 x i8> %r
|
|
}
|
|
|
|
declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
|
|
|
define <16 x i8> @__avg_down_int8(<16 x i8>, <16 x i8>) nounwind readnone alwaysinline {
|
|
%r = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %0, <16 x i8> %1)
|
|
ret <16 x i8> %r
|
|
}
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
|
|
|
define <16 x i16> @__avg_up_uint16(<16 x i16>, <16 x i16>) nounwind readnone alwaysinline {
|
|
v16tov8(i16, %0, %a0, %b0)
|
|
v16tov8(i16, %1, %a1, %b1)
|
|
%r0 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %a0, <8 x i16> %a1)
|
|
%r1 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %b0, <8 x i16> %b1)
|
|
v8tov16(i16, %r0, %r1, %r)
|
|
ret <16 x i16> %r
|
|
}
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
|
|
|
define <16 x i16> @__avg_up_int16(<16 x i16>, <16 x i16>) nounwind readnone alwaysinline {
|
|
v16tov8(i16, %0, %a0, %b0)
|
|
v16tov8(i16, %1, %a1, %b1)
|
|
%r0 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %a0, <8 x i16> %a1)
|
|
%r1 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %b0, <8 x i16> %b1)
|
|
v8tov16(i16, %r0, %r1, %r)
|
|
ret <16 x i16> %r
|
|
}
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
|
|
|
define <16 x i16> @__avg_down_uint16(<16 x i16>, <16 x i16>) nounwind readnone alwaysinline {
|
|
v16tov8(i16, %0, %a0, %b0)
|
|
v16tov8(i16, %1, %a1, %b1)
|
|
%r0 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %a0, <8 x i16> %a1)
|
|
%r1 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %b0, <8 x i16> %b1)
|
|
v8tov16(i16, %r0, %r1, %r)
|
|
ret <16 x i16> %r
|
|
}
|
|
|
|
declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
|
|
|
define <16 x i16> @__avg_down_int16(<16 x i16>, <16 x i16>) nounwind readnone alwaysinline {
|
|
v16tov8(i16, %0, %a0, %b0)
|
|
v16tov8(i16, %1, %a1, %b1)
|
|
%r0 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %a0, <8 x i16> %a1)
|
|
%r1 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %b0, <8 x i16> %b1)
|
|
v8tov16(i16, %r0, %r1, %r)
|
|
ret <16 x i16> %r
|
|
}
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; reciprocals in double precision, if supported
|
|
|
|
rsqrtd_decl()
|
|
rcpd_decl()
|
|
|
|
transcendetals_decl()
|
|
trigonometry_decl()
|
|
saturation_arithmetic()
|