Revert "Fix for Revision 269218"

builtins.cpp

@@ -445,8 +445,6 @@ lSetInternalFunctions(llvm::Module *module) {
         "__broadcast_i32",
         "__broadcast_i64",
         "__broadcast_i8",
-        "__cast_mask_to_i1",
-        "__cast_mask_to_i16",
         "__ceil_uniform_double",
         "__ceil_uniform_float",
         "__ceil_varying_double",
@@ -484,8 +482,6 @@ lSetInternalFunctions(llvm::Module *module) {
         "__extract_float",
         "__extract_double",
 //#endif /* ISPC_NVPTX_ENABLED */
-        "__extract_mask_low",
-        "__extract_mask_hi",
         "__fastmath",
         "__float_to_half_uniform",
         "__float_to_half_varying",

builtins/target-avx512-common.ll

@@ -29,7 +29,7 @@
 ;;   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 ;;   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
 
-define(`MASK',`i8')
+define(`MASK',`i1')
 define(`HAVE_GATHER',`1')
 define(`HAVE_SCATTER',`1')
 
@@ -50,33 +50,6 @@ define_shuffles()
 
 aossoa()
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; Stub for mask conversion. LLVM's intrinsics want i1 mask, but we use i8
-
-define <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %mask) alwaysinline {
-  %mask_vec_i1 = icmp ne <WIDTH x MASK> %mask, const_vector(MASK, 0)
-  ret <WIDTH x i1> %mask_vec_i1
-}
-
-define i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask) alwaysinline {
-  %mask_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %mask)
-  %mask_i16 = bitcast <WIDTH x i1> %mask_i1 to i16
-  ret i16 %mask_i16
-}
-
-define i8 @__extract_mask_low (<WIDTH x MASK> %mask) alwaysinline {
-  %mask_i16 = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
-  %mask_low = trunc i16 %mask_i16 to i8 
-  ret i8 %mask_low
-}
-
-define i8 @__extract_mask_hi (<WIDTH x MASK> %mask) alwaysinline {
-  %mask_i16 = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
-  %mask_shifted = lshr i16 %mask_i16, 8
-  %mask_hi = trunc i16 %mask_shifted to i8
-  ret i8 %mask_hi
-}
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; half conversion routines
 
@@ -628,31 +601,29 @@ include(`svml.m4')
 svml_stubs(float,f,WIDTH)
 svml_stubs(double,d,WIDTH)
 
-
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; reductions
 
-define i64 @__movmsk(<WIDTH x MASK> %mask) nounwind readnone alwaysinline {
+define i64 @__movmsk(<WIDTH x i1>) nounwind readnone alwaysinline {
-  %intmask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %intmask = bitcast <WIDTH x i1> %0 to i16
   %res = zext i16 %intmask to i64
   ret i64 %res
 }
 
-define i1 @__any(<WIDTH x MASK> %mask) nounwind readnone alwaysinline {
+define i1 @__any(<WIDTH x i1>) nounwind readnone alwaysinline {
-  %intmask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %intmask = bitcast <WIDTH x i1> %0 to i16
   %res = icmp ne i16 %intmask, 0
   ret i1 %res
 }
 
-define i1 @__all(<WIDTH x MASK> %mask) nounwind readnone alwaysinline {
+define i1 @__all(<WIDTH x i1>) nounwind readnone alwaysinline {
-  %intmask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %intmask = bitcast <WIDTH x i1> %0 to i16
   %res = icmp eq i16 %intmask, 65535
   ret i1 %res
 }
 
-define i1 @__none(<WIDTH x MASK> %mask) nounwind readnone alwaysinline {
+define i1 @__none(<WIDTH x i1>) nounwind readnone alwaysinline {
-  %intmask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %intmask = bitcast <WIDTH x i1> %0 to i16
   %res = icmp eq i16 %intmask, 0
   ret i1 %res
 }
@@ -828,16 +799,19 @@ masked_load(i8,  1)
 masked_load(i16, 2)
 
 declare <16 x i32> @llvm.x86.avx512.mask.loadu.d.512(i8*, <16 x i32>, i16)
-define <16 x i32> @__masked_load_i32(i8 * %ptr, <WIDTH x MASK> %mask) nounwind alwaysinline {
+define <16 x i32> @__masked_load_i32(i8 * %ptr, <16 x i1> %mask) nounwind alwaysinline {
-  %mask_i16 = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
   %res = call <16 x i32> @llvm.x86.avx512.mask.loadu.d.512(i8* %ptr, <16 x i32> zeroinitializer, i16 %mask_i16)
   ret <16 x i32> %res
 }
 
 declare <8 x i64> @llvm.x86.avx512.mask.loadu.q.512(i8*, <8 x i64>, i8)
-define <16 x i64> @__masked_load_i64(i8 * %ptr, <WIDTH x MASK> %mask) nounwind alwaysinline {
+define <16 x i64> @__masked_load_i64(i8 * %ptr, <16 x i1> %mask) nounwind alwaysinline {
-  %mask_lo_i8 = call i8 @__extract_mask_low (<WIDTH x MASK> %mask) 
+  %mask_i16 = bitcast <16 x i1> %mask to i16
-  %mask_hi_i8 = call i8 @__extract_mask_hi (<WIDTH x MASK> %mask)
+  %mask_lo_i8 = trunc i16 %mask_i16 to i8
+  %mask_hi = shufflevector <16 x i1> %mask, <16 x i1> undef,
+                           <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %mask_hi_i8 = bitcast <8 x i1> %mask_hi to i8
   
   %ptr_d = bitcast i8* %ptr to <16 x i64>*
   %ptr_hi = getelementptr PTR_OP_ARGS(`<16 x i64>') %ptr_d, i32 0, i32 8
@@ -854,16 +828,19 @@ define <16 x i64> @__masked_load_i64(i8 * %ptr, <WIDTH x MASK> %mask) nounwind a
 
 
 declare <16 x float> @llvm.x86.avx512.mask.loadu.ps.512(i8*, <16 x float>, i16)
-define <16 x float> @__masked_load_float(i8 * %ptr, <WIDTH x MASK> %mask) readonly alwaysinline {
+define <16 x float> @__masked_load_float(i8 * %ptr, <16 x i1> %mask) readonly alwaysinline {
-  %mask_i16 = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
   %res = call <16 x float> @llvm.x86.avx512.mask.loadu.ps.512(i8* %ptr, <16 x float> zeroinitializer, i16 %mask_i16)
   ret <16 x float> %res
 }
 
 declare <8 x double> @llvm.x86.avx512.mask.loadu.pd.512(i8*, <8 x double>, i8)
-define <16 x double> @__masked_load_double(i8 * %ptr, <WIDTH x MASK> %mask) readonly alwaysinline {
+define <16 x double> @__masked_load_double(i8 * %ptr, <16 x i1> %mask) readonly alwaysinline {
-  %mask_lo_i8 = call i8 @__extract_mask_low (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
-  %mask_hi_i8 = call i8 @__extract_mask_hi (<WIDTH x MASK> %mask)
+  %mask_lo_i8 = trunc i16 %mask_i16 to i8
+  %mask_hi = shufflevector <16 x i1> %mask, <16 x i1> undef,
+                           <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %mask_hi_i8 = bitcast <8 x i1> %mask_hi to i8
 
   %ptr_d = bitcast i8* %ptr to <16 x double>*
   %ptr_hi = getelementptr PTR_OP_ARGS(`<16 x double>') %ptr_d, i32 0, i32 8
@@ -883,17 +860,20 @@ gen_masked_store(i8) ; llvm.x86.sse2.storeu.dq
 gen_masked_store(i16)
 
 declare void @llvm.x86.avx512.mask.storeu.d.512(i8*, <16 x i32>, i16)
-define void @__masked_store_i32(<16 x i32>* nocapture, <16 x i32> %v, <WIDTH x MASK> %mask) nounwind alwaysinline {
+define void @__masked_store_i32(<16 x i32>* nocapture, <16 x i32> %v, <16 x i1> %mask) nounwind alwaysinline {
-  %mask_i16 = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
   %ptr_i8 = bitcast <16 x i32>* %0 to i8*
   call void @llvm.x86.avx512.mask.storeu.d.512(i8* %ptr_i8, <16 x i32> %v, i16 %mask_i16)
   ret void
 }
 
 declare void @llvm.x86.avx512.mask.storeu.q.512(i8*, <8 x i64>, i8)
-define void @__masked_store_i64(<16 x i64>* nocapture, <16 x i64> %v, <WIDTH x MASK> %mask) nounwind alwaysinline {
+define void @__masked_store_i64(<16 x i64>* nocapture, <16 x i64> %v, <16 x i1> %mask) nounwind alwaysinline {
-  %mask_lo_i8 = call i8 @__extract_mask_low (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
-  %mask_hi_i8 = call i8 @__extract_mask_hi (<WIDTH x MASK> %mask)
+  %mask_lo_i8 = trunc i16 %mask_i16 to i8
+  %mask_hi = shufflevector <16 x i1> %mask, <16 x i1> undef,
+                           <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %mask_hi_i8 = bitcast <8 x i1> %mask_hi to i8
 
   %ptr_i8 = bitcast <16 x i64>* %0 to i8*
   %ptr_lo = getelementptr PTR_OP_ARGS(`<16 x i64>') %0, i32 0, i32 8
@@ -910,18 +890,20 @@ define void @__masked_store_i64(<16 x i64>* nocapture, <16 x i64> %v, <WIDTH x M
 }
 
 declare void @llvm.x86.avx512.mask.storeu.ps.512(i8*, <16 x float>, i16 )
-define void @__masked_store_float(<16 x float>* nocapture, <16 x float> %v, <WIDTH x MASK> %mask) nounwind alwaysinline {
+define void @__masked_store_float(<16 x float>* nocapture, <16 x float> %v, <16 x i1> %mask) nounwind alwaysinline {
-  %mask_i16 = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
-
   %ptr_i8 = bitcast <16 x float>* %0 to i8*
   call void @llvm.x86.avx512.mask.storeu.ps.512(i8* %ptr_i8, <16 x float> %v, i16 %mask_i16)
   ret void
 }
 
 declare void @llvm.x86.avx512.mask.storeu.pd.512(i8*, <8 x double>, i8)
-define void @__masked_store_double(<16 x double>* nocapture, <16 x double> %v, <WIDTH x MASK> %mask) nounwind alwaysinline {
+define void @__masked_store_double(<16 x double>* nocapture, <16 x double> %v, <16 x i1> %mask) nounwind alwaysinline {
-  %mask_lo_i8 = call i8 @__extract_mask_low (<WIDTH x MASK> %mask)
+  %mask_i16 = bitcast <16 x i1> %mask to i16
-  %mask_hi_i8 = call i8 @__extract_mask_hi (<WIDTH x MASK> %mask)
+  %mask_lo_i8 = trunc i16 %mask_i16 to i8
+  %mask_hi = shufflevector <16 x i1> %mask, <16 x i1> undef,
+                           <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %mask_hi_i8 = bitcast <8 x i1> %mask_hi to i8
 
   %ptr_i8 = bitcast <16 x double>* %0 to i8*
   %ptr_lo = getelementptr PTR_OP_ARGS(`<16 x double>') %0, i32 0, i32 8
@@ -938,55 +920,49 @@ define void @__masked_store_double(<16 x double>* nocapture, <16 x double> %v, <
 }
 
 define void @__masked_store_blend_i8(<16 x i8>* nocapture, <16 x i8>, 
-                                     <WIDTH x MASK>) nounwind alwaysinline {
+                                     <16 x i1>) nounwind alwaysinline {
   %v = load PTR_OP_ARGS(`<16 x i8> ')  %0
-  %mask_vec_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %2)
+  %v1 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> %v
-  %v1 = select <WIDTH x i1> %mask_vec_i1, <16 x i8> %1, <16 x i8> %v
   store <16 x i8> %v1, <16 x i8> * %0
   ret void
 }
 
 define void @__masked_store_blend_i16(<16 x i16>* nocapture, <16 x i16>, 
-                                      <WIDTH x MASK>) nounwind alwaysinline {
+                                      <16 x i1>) nounwind alwaysinline {
   %v = load PTR_OP_ARGS(`<16 x i16> ')  %0
-  %mask_vec_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %2)
+  %v1 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %v
-  %v1 = select <WIDTH x i1> %mask_vec_i1, <16 x i16> %1, <16 x i16> %v
   store <16 x i16> %v1, <16 x i16> * %0
   ret void
 }
 
 define void @__masked_store_blend_i32(<16 x i32>* nocapture, <16 x i32>, 
-                                      <WIDTH x MASK>) nounwind alwaysinline {
+                                      <16 x i1>) nounwind alwaysinline {
   %v = load PTR_OP_ARGS(`<16 x i32> ')  %0
-  %mask_vec_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %2)
+  %v1 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %v
-  %v1 = select <WIDTH x i1> %mask_vec_i1, <16 x i32> %1, <16 x i32> %v
   store <16 x i32> %v1, <16 x i32> * %0
   ret void
 }
 
 define void @__masked_store_blend_float(<16 x float>* nocapture, <16 x float>, 
-                                        <WIDTH x MASK>) nounwind alwaysinline {
+                                        <16 x i1>) nounwind alwaysinline {
   %v = load PTR_OP_ARGS(`<16 x float> ')  %0
-  %mask_vec_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %2)
+  %v1 = select <16 x i1> %2, <16 x float> %1, <16 x float> %v
-  %v1 = select <WIDTH x i1> %mask_vec_i1, <16 x float> %1, <16 x float> %v
   store <16 x float> %v1, <16 x float> * %0
   ret void
 }
 
 define void @__masked_store_blend_i64(<16 x i64>* nocapture,
-                            <16 x i64>, <WIDTH x MASK>) nounwind alwaysinline {
+                            <16 x i64>, <16 x i1>) nounwind alwaysinline {
   %v = load PTR_OP_ARGS(`<16 x i64> ')  %0
-  %mask_vec_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %2)
+  %v1 = select <16 x i1> %2, <16 x i64> %1, <16 x i64> %v
-  %v1 = select <WIDTH x i1> %mask_vec_i1, <16 x i64> %1, <16 x i64> %v
   store <16 x i64> %v1, <16 x i64> * %0
   ret void
 }
 
 define void @__masked_store_blend_double(<16 x double>* nocapture,
-                            <16 x double>, <WIDTH x MASK>) nounwind alwaysinline {
+                            <16 x double>, <16 x i1>) nounwind alwaysinline {
   %v = load PTR_OP_ARGS(`<16 x double> ')  %0
-  %mask_vec_i1 = call <WIDTH x i1> @__cast_mask_to_i1 (<WIDTH x MASK> %2)
+  %v1 = select <16 x i1> %2, <16 x double> %1, <16 x double> %v
-  %v1 = select <WIDTH x i1> %mask_vec_i1, <16 x double> %1, <16 x double> %v
   store <16 x double> %v1, <16 x double> * %0
   ret void
 }
@@ -1003,16 +979,16 @@ gen_gather(i16)
 ;; gather - i32
 declare <16 x i32> @llvm.x86.avx512.gather.dpi.512(<16 x i32>, i8*, <16 x i32>, i16, i32)
 define <16 x i32> 
-@__gather_base_offsets32_i32(i8 * %ptr, i32 %offset_scale, <16 x i32> %offsets, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather_base_offsets32_i32(i8 * %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   %res =  call <16 x i32> @llvm.x86.avx512.gather.dpi.512 (<16 x i32> undef, i8* %ptr, <16 x i32> %offsets, i16 %mask, i32 %offset_scale)
   ret <16 x i32> %res
 }
 
 declare <8 x i32> @llvm.x86.avx512.gather.qpi.512 (<8 x i32>, i8*, <8 x i64>, i8, i32)
 define <16 x i32> 
-@__gather_base_offsets64_i32(i8 * %ptr, i32 %offset_scale, <16 x i64> %offsets, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather_base_offsets64_i32(i8 * %ptr, i32 %offset_scale, <16 x i64> %offsets, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %scalarMask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask) 
+  %scalarMask = bitcast <16 x i1> %vecmask to i16 
   %scalarMask1 = trunc i16 %scalarMask to i8 
   %scalarMask2Tmp = lshr i16 %scalarMask, 8
   %scalarMask2 = trunc i16  %scalarMask2Tmp to i8 
@@ -1025,14 +1001,14 @@ define <16 x i32>
 }
 
 define <16 x i32> 
-@__gather32_i32(<16 x i32> %ptrs, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather32_i32(<16 x i32> %ptrs, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %res = call <16 x i32> @__gather_base_offsets32_i32(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <WIDTH x MASK> %vecmask)
+  %res = call <16 x i32> @__gather_base_offsets32_i32(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <16 x i1> %vecmask)
   ret <16 x i32> %res
 }
 
 define <16 x i32> 
-@__gather64_i32(<16x i64> %ptrs, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather64_i32(<16x i64> %ptrs, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %res = call <16 x i32> @__gather_base_offsets64_i32(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <WIDTH x MASK> %vecmask)
+  %res = call <16 x i32> @__gather_base_offsets64_i32(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <16 x i1> %vecmask)
   ret <16 x i32> %res
 }
 
@@ -1042,16 +1018,16 @@ gen_gather(i64)
 ;; gather - float
 declare <16 x float> @llvm.x86.avx512.gather.dps.512 (<16 x float>, i8*, <16 x i32>, i16, i32)
 define <16 x float>
-@__gather_base_offsets32_float(i8 * %ptr, i32 %offset_scale, <16 x i32> %offsets, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather_base_offsets32_float(i8 * %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   %res = call <16 x float> @llvm.x86.avx512.gather.dps.512 (<16 x float> undef, i8* %ptr, <16 x i32>%offsets, i16 %mask, i32 %offset_scale)
   ret <16 x float> %res
 }
 
 declare <8 x float> @llvm.x86.avx512.gather.qps.512 (<8 x float>, i8*, <8 x i64>, i8, i32)
 define <16 x float>
-@__gather_base_offsets64_float(i8 * %ptr, i32 %offset_scale, <16 x i64> %offsets, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather_base_offsets64_float(i8 * %ptr, i32 %offset_scale, <16 x i64> %offsets, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   %mask_shifted = lshr i16 %mask, 8
   %mask_lo = trunc i16 %mask to i8 
   %mask_hi = trunc i16 %mask_shifted to i8 
@@ -1064,14 +1040,14 @@ define <16 x float>
 }
 
 define <16 x float> 
-@__gather32_float(<16 x i32> %ptrs, <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather32_float(<16 x i32> %ptrs, <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %res = call <16 x float> @__gather_base_offsets32_float(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <WIDTH x MASK> %vecmask)
+  %res = call <16 x float> @__gather_base_offsets32_float(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <16 x i1> %vecmask)
   ret <16 x float> %res
 }
 
 define <16 x float> 
-@__gather64_float(<16 x i64> %ptrs,  <WIDTH x MASK> %vecmask) nounwind readonly alwaysinline {
+@__gather64_float(<16 x i64> %ptrs,  <16 x i1> %vecmask) nounwind readonly alwaysinline {
-  %res = call <16 x float> @__gather_base_offsets64_float(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <WIDTH x MASK> %vecmask)
+  %res = call <16 x float> @__gather_base_offsets64_float(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <16 x i1> %vecmask)
   ret <16 x float> %res
 }
 
@@ -1081,16 +1057,16 @@ gen_gather(double)
 
 define(`scatterbo32_64', `
 define void @__scatter_base_offsets32_$1(i8* %ptr, i32 %scale, <WIDTH x i32> %offsets,
-                                         <WIDTH x $1> %vals, <WIDTH x MASK> %mask) nounwind {
+                                         <WIDTH x $1> %vals, <WIDTH x i1> %mask) nounwind {
   call void @__scatter_factored_base_offsets32_$1(i8* %ptr, <16 x i32> %offsets,
-      i32 %scale, <16 x i32> zeroinitializer, <16 x $1> %vals, <WIDTH x MASK> %mask)
+      i32 %scale, <16 x i32> zeroinitializer, <16 x $1> %vals, <WIDTH x i1> %mask)
   ret void
 }
 
 define void @__scatter_base_offsets64_$1(i8* %ptr, i32 %scale, <WIDTH x i64> %offsets,
-                                         <WIDTH x $1> %vals, <WIDTH x MASK> %mask) nounwind {
+                                         <WIDTH x $1> %vals, <WIDTH x i1> %mask) nounwind {
   call void @__scatter_factored_base_offsets64_$1(i8* %ptr, <16 x i64> %offsets,
-      i32 %scale, <16 x i64> zeroinitializer, <16 x $1> %vals, <WIDTH x MASK> %mask)
+      i32 %scale, <16 x i64> zeroinitializer, <16 x $1> %vals, <WIDTH x i1> %mask)
   ret void
 } 
 ')
@@ -1106,16 +1082,16 @@ gen_scatter(i16)
 ;; scatter - i32
 declare void @llvm.x86.avx512.scatter.dpi.512 (i8*, i16, <16 x i32>, <16 x i32>, i32)
 define void 
-@__scatter_base_offsets32_i32(i8* %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x i32> %vals, <WIDTH x MASK> %vecmask) nounwind {
+@__scatter_base_offsets32_i32(i8* %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x i32> %vals, <16 x i1> %vecmask) nounwind {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   call void @llvm.x86.avx512.scatter.dpi.512 (i8* %ptr, i16 %mask, <16 x i32> %offsets, <16 x i32> %vals, i32 %offset_scale)
   ret void
 }
 
 declare void @llvm.x86.avx512.scatter.qpi.512 (i8*, i8, <8 x i64>, <8 x i32>, i32)
 define void 
-@__scatter_base_offsets64_i32(i8* %ptr, i32 %offset_scale, <16 x i64> %offsets, <16 x i32> %vals, <WIDTH x MASK> %vecmask) nounwind {
+@__scatter_base_offsets64_i32(i8* %ptr, i32 %offset_scale, <16 x i64> %offsets, <16 x i32> %vals, <16 x i1> %vecmask) nounwind {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   %mask_shifted = lshr i16 %mask, 8
   %mask_lo = trunc i16 %mask to i8 
   %mask_hi = trunc i16 %mask_shifted to i8 
@@ -1129,14 +1105,14 @@ define void
 } 
 
 define void 
-@__scatter32_i32(<16 x i32> %ptrs, <16 x i32> %values, <WIDTH x MASK> %vecmask) nounwind alwaysinline {
+@__scatter32_i32(<16 x i32> %ptrs, <16 x i32> %values, <16 x i1> %vecmask) nounwind alwaysinline {
-  call void @__scatter_base_offsets32_i32(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <16 x i32> %values, <WIDTH x MASK> %vecmask)
+  call void @__scatter_base_offsets32_i32(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <16 x i32> %values, <16 x i1> %vecmask)
   ret void
 }
 
 define void 
-@__scatter64_i32(<16 x i64> %ptrs, <16 x i32> %values, <WIDTH x MASK> %vecmask) nounwind alwaysinline {
+@__scatter64_i32(<16 x i64> %ptrs, <16 x i32> %values, <16 x i1> %vecmask) nounwind alwaysinline {
-  call void @__scatter_base_offsets64_i32(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <16 x i32> %values, <WIDTH x MASK> %vecmask)
+  call void @__scatter_base_offsets64_i32(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <16 x i32> %values, <16 x i1> %vecmask)
   ret void
 }
 
@@ -1147,16 +1123,16 @@ gen_scatter(i64)
 ;; scatter - float
 declare void @llvm.x86.avx512.scatter.dps.512 (i8*, i16, <16 x i32>, <16 x float>, i32)
 define void 
-@__scatter_base_offsets32_float(i8* %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x float> %vals, <WIDTH x MASK> %vecmask) nounwind {
+@__scatter_base_offsets32_float(i8* %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x float> %vals, <16 x i1> %vecmask) nounwind {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   call void @llvm.x86.avx512.scatter.dps.512 (i8* %ptr, i16 %mask, <16 x i32> %offsets, <16 x float> %vals, i32 %offset_scale)
   ret void
 }
 
 declare void @llvm.x86.avx512.scatter.qps.512 (i8*, i8, <8 x i64>, <8 x float>, i32)
 define void 
-@__scatter_base_offsets64_float(i8* %ptr, i32 %offset_scale, <16 x i64> %offsets, <16 x float> %vals, <WIDTH x MASK> %vecmask) nounwind {
+@__scatter_base_offsets64_float(i8* %ptr, i32 %offset_scale, <16 x i64> %offsets, <16 x float> %vals, <16 x i1> %vecmask) nounwind {
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %vecmask)
+  %mask = bitcast <16 x i1> %vecmask to i16
   %mask_shifted = lshr i16 %mask, 8
   %mask_lo = trunc i16 %mask to i8 
   %mask_hi = trunc i16 %mask_shifted to i8 
@@ -1170,14 +1146,14 @@ define void
 } 
 
 define void 
-@__scatter32_float(<16 x i32> %ptrs, <16 x float> %values, <WIDTH x MASK> %vecmask) nounwind alwaysinline {
+@__scatter32_float(<16 x i32> %ptrs, <16 x float> %values, <16 x i1> %vecmask) nounwind alwaysinline {
-  call void @__scatter_base_offsets32_float(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <16 x float> %values, <WIDTH x MASK> %vecmask)
+  call void @__scatter_base_offsets32_float(i8 * zeroinitializer, i32 1, <16 x i32> %ptrs, <16 x float> %values, <16 x i1> %vecmask)
   ret void
 }
 
 define void 
-@__scatter64_float(<16 x i64> %ptrs, <16 x float> %values, <WIDTH x MASK> %vecmask) nounwind alwaysinline {
+@__scatter64_float(<16 x i64> %ptrs, <16 x float> %values, <16 x i1> %vecmask) nounwind alwaysinline {
-  call void @__scatter_base_offsets64_float(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <16 x float> %values, <WIDTH x MASK> %vecmask)
+  call void @__scatter_base_offsets64_float(i8 * zeroinitializer, i32 1, <16 x i64> %ptrs, <16 x float> %values, <16 x i1> %vecmask)
   ret void
 }
 
@@ -1191,10 +1167,10 @@ gen_scatter(double)
 declare <16 x i32> @llvm.x86.avx512.mask.expand.load.d.512(i8* %addr, <16 x i32> %data, i16 %mask)
 
 define i32 @__packed_load_active(i32 * %startptr, <16 x i32> * %val_ptr,
-                                 <WIDTH x MASK> %full_mask) nounwind alwaysinline {
+                                 <16 x i1> %full_mask) nounwind alwaysinline {
   %addr = bitcast i32* %startptr to i8*
   %data = load PTR_OP_ARGS(`<16 x i32> ') %val_ptr
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %full_mask)
+  %mask = bitcast <16 x i1> %full_mask to i16
   %store_val = call <16 x i32> @llvm.x86.avx512.mask.expand.load.d.512(i8* %addr, <16 x i32> %data, i16 %mask)
   store <16 x i32> %store_val, <16 x i32> * %val_ptr
   %mask_i32 = zext i16 %mask to i32
@@ -1205,9 +1181,9 @@ define i32 @__packed_load_active(i32 * %startptr, <16 x i32> * %val_ptr,
 declare void @llvm.x86.avx512.mask.compress.store.d.512(i8* %addr, <16 x i32> %data, i16 %mask)
 
 define i32 @__packed_store_active(i32 * %startptr, <16 x i32> %vals,
-                                   <WIDTH x MASK> %full_mask) nounwind alwaysinline {
+                                   <16 x i1> %full_mask) nounwind alwaysinline {
   %addr = bitcast i32* %startptr to i8*
-  %mask = call i16 @__cast_mask_to_i16 (<WIDTH x MASK> %full_mask)
+  %mask = bitcast <16 x i1> %full_mask to i16
   call void @llvm.x86.avx512.mask.compress.store.d.512(i8* %addr, <16 x i32> %vals, i16 %mask)
   %mask_i32 = zext i16 %mask to i32
   %res = call i32 @llvm.ctpop.i32(i32 %mask_i32)
@@ -1215,9 +1191,9 @@ define i32 @__packed_store_active(i32 * %startptr, <16 x i32> %vals,
 }
 
 define i32 @__packed_store_active2(i32 * %startptr, <16 x i32> %vals,
-                                   <WIDTH x MASK> %full_mask) nounwind alwaysinline {
+                                   <16 x i1> %full_mask) nounwind alwaysinline {
   %res = call i32 @__packed_store_active(i32 * %startptr, <16 x i32> %vals,
-                                   <WIDTH x MASK> %full_mask)
+                                   <16 x i1> %full_mask)
   ret i32 %res
 }
 

cbackend.cpp

@@ -2337,7 +2337,7 @@ static SpecialGlobalClass getGlobalVariableClass(const llvm::GlobalVariable *GV)
 
   // Otherwise, if it is other metadata, don't print it.  This catches things
   // like debug information.
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5 && ISPC_LLVM_VERSION <= ISPC_LLVM_3_8 /* LLVM 3.5-3.8 */
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5 /* LLVM 3.5+ */
   // Here we compare char *
   if (!strcmp(GV->getSection(), "llvm.metadata"))
 #else

ctx.cpp

@@ -425,7 +425,6 @@ FunctionEmitContext::FunctionEmitContext(Function *func, Symbol *funSym,
                                          isStatic,           true, /* is defn */
                                          firstLine,          flags,
                                          isOptimized);
-        llvmFunction->setSubprogram(diSubprogram);
 #endif
 
         /* And start a scope representing the initial function scope */

docs/ReleaseNotes.txt

@@ -1,11 +1,3 @@
-=== v1.9.1 === (8 July 2016)
-
-An ISPC update with new native AVX512 target for future Xeon CPUs and
-improvements for debugging, including new switch --dwarf-version to support
-debugging on old systems.
-
-The release is based on patched version LLVM 3.8.
-
 === v1.9.0 === (12 Feb 2016)
 
 An ISPC release with AVX512 (KNL flavor) support and a number of bug fixes,

docs/ispc.rst

@@ -53,7 +53,6 @@ Contents:
   + `Updating ISPC Programs For Changes In ISPC 1.7.0`_
   + `Updating ISPC Programs For Changes In ISPC 1.8.2`_
   + `Updating ISPC Programs For Changes In ISPC 1.9.0`_
-  + `Updating ISPC Programs For Changes In ISPC 1.9.1`_
 
 * `Getting Started with ISPC`_
 
@@ -346,12 +345,6 @@ Updating ISPC Programs For Changes In ISPC 1.9.0
 The release doesn't contains language changes, which may affect compatibility with
 older versions. It introduces new AVX512 target: avx512knl-i32x16.
 
-Updating ISPC Programs For Changes In ISPC 1.9.1
-------------------------------------------------
-
-The release doesn't contains language changes, which may affect compatibility with
-older versions. It introduces new AVX512 target: avx512skx-i32x16.
-
 
 Getting Started with ISPC
 =========================
@@ -585,7 +578,6 @@ avx, avx1    AVX (2010-2011 era Intel CPUs)
 avx1.1       AVX 1.1 (2012 era "Ivybridge" Intel CPUs)
 avx2         AVX 2 target (2013- Intel "Haswell" CPUs)
 avx512knl    AVX 512 target (Xeon Phi chips codename Knights Landing)
-avx512skx    AVX 512 target (future Xeon CPUs)
 neon         ARM NEON
 sse2         SSE2 (early 2000s era x86 CPUs)
 sse4         SSE4 (generally 2008-2010 Intel CPUs)
@@ -815,7 +807,7 @@ preprocessor runs:
   * - ISPC
     - 1
     - Detecting that the ``ispc`` compiler is processing the file
-  * - ISPC_TARGET_{NEON_8, NEON_16, NEON_32, SSE2, SSE4, AVX, AVX11, AVX2, AVX512KNL, AVX512SKX, GENERIC}
+  * - ISPC_TARGET_{NEON_8,NEON_16,NEON_32,SSE2,SSE4,AVX,AVX11,AVX2,AVX512KNL,GENERIC}
     - 1
     - One of these will be set, depending on the compilation target.
   * - ISPC_POINTER_SIZE

docs/news.rst

@@ -2,16 +2,6 @@
 ispc News
 =========
 
-ispc 1.9.1 is Released
-----------------------
-
-An ``ispc`` release with new native AVX512 target for future Xeon CPUs and
-improvements for debugging. Release is based on patched version LLVM 3.8 backend.
-
-For more details, please check `Release Notes`_.
-
-.. _Release Notes: https://github.com/ispc/ispc/blob/master/docs/ReleaseNotes.txt
-
 ispc 1.9.0 is Released
 ----------------------
 

doxygen.cfg

@@ -31,7 +31,7 @@ PROJECT_NAME           = "Intel SPMD Program Compiler"
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.
 
-PROJECT_NUMBER         = 1.9.1
+PROJECT_NUMBER         = 1.9.1dev
 
 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.

examples/tasksys.cpp

@@ -47,7 +47,6 @@
     - Cilk Plus (ISPC_USE_CILK)
     - TBB (ISPC_USE_TBB_TASK_GROUP, ISPC_USE_TBB_PARALLEL_FOR)
     - OpenMP (ISPC_USE_OMP)
-    - HPX (ISPC_USE_HPX)
 
   The task system implementation can be selected at compile time, by defining 
   the appropriate preprocessor symbol on the command line (for e.g.: -D ISPC_USE_TBB).
@@ -70,20 +69,13 @@
   the machine, but less so when there are other tasks that need running on the machine.
 
 #define ISPC_USE_CREW
-#define ISPC_USE_HPX
-  The HPX model requires the HPX runtime environment to be set up. This can be
-  done manually, e.g. with hpx::init, or by including hpx/hpx_main.hpp which
-  uses the main() function as entry point and sets up the runtime system.
-  Number of threads can be specified as commandline parameter with
-  --hpx:threads, use "all" to spawn one thread per processing unit.
 
 */
 
 #if !(defined ISPC_USE_CONCRT          || defined ISPC_USE_GCD              || \
       defined ISPC_USE_PTHREADS        || defined ISPC_USE_PTHREADS_FULLY_SUBSCRIBED || \
       defined ISPC_USE_TBB_TASK_GROUP  || defined ISPC_USE_TBB_PARALLEL_FOR || \
-      defined ISPC_USE_OMP             || defined ISPC_USE_CILK             || \
+      defined ISPC_USE_OMP             || defined ISPC_USE_CILK             )
-      defined ISPC_USE_HPX)
 
     // If no task model chosen from the compiler cmdline, pick a reasonable default
     #if defined(_WIN32) || defined(_WIN64)
@@ -165,10 +157,6 @@
 #ifdef ISPC_USE_OMP
   #include <omp.h>
 #endif // ISPC_USE_OMP
-#ifdef ISPC_USE_HPX
-#include <hpx/include/async.hpp>
-#include <hpx/lcos/wait_all.hpp>
-#endif // ISPC_USE_HPX
 #ifdef ISPC_IS_LINUX
   #include <malloc.h>
 #endif // ISPC_IS_LINUX
@@ -517,20 +505,6 @@ private:
 
 #endif // ISPC_USE_TBB_TASK_GROUP
 
-#ifdef ISPC_USE_HPX
-
-class TaskGroup : public TaskGroupBase {
-public:
-    void Launch(int baseIndex, int count);
-    void Sync();
-private:
-    std::vector<hpx::future<void>> futures;
-};
-
-#endif // ISPC_USE_HPX
-
-///////////////////////////////////////////////////////////////////////////
-
 ///////////////////////////////////////////////////////////////////////////
 // Grand Central Dispatch
 
@@ -1074,33 +1048,6 @@ TaskGroup::Sync() {
 
 #endif // ISPC_USE_TBB_TASK_GROUP
 
-///////////////////////////////////////////////////////////////////////////
-// ISPC_USE_HPX
-
-#ifdef ISPC_USE_HPX
-
-static void
-InitTaskSystem() {
-}
-
-inline void
-TaskGroup::Launch(int baseIndex, int count) {
-    for (int i = 0; i < count; ++i) {
-        TaskInfo *ti = GetTaskInfo(baseIndex + i);
-        int threadIndex = i;
-        int threadCount = count;
-        futures.push_back(hpx::async(ti->func, ti->data, threadIndex, threadCount, ti->taskIndex, ti->taskCount(),
-            ti->taskIndex0(), ti->taskIndex1(), ti->taskIndex2(),
-            ti->taskCount0(), ti->taskCount1(), ti->taskCount2()));
-    }
-}
-
-inline void
-TaskGroup::Sync() {
-    hpx::wait_all(futures);
-    futures.clear();
-}
-#endif
 ///////////////////////////////////////////////////////////////////////////
 
 #ifndef ISPC_USE_PTHREADS_FULLY_SUBSCRIBED

ispc.cpp

@@ -934,7 +934,7 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic, boo
         // ?? this->m_dataTypeWidth = 32;
         this->m_vectorWidth = 16;
         this->m_maskingIsFree = true;
-        this->m_maskBitCount = 8;
+        this->m_maskBitCount = 1;
         this->m_hasHalf = true;
         this->m_hasRand = true;
         this->m_hasGather = this->m_hasScatter = true;
@@ -954,7 +954,7 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic, boo
         // ?? this->m_dataTypeWidth = 32;
         this->m_vectorWidth = 16;
         this->m_maskingIsFree = true;
-        this->m_maskBitCount = 8;
+        this->m_maskBitCount = 1;
         this->m_hasHalf = true;
         this->m_hasRand = true;
         this->m_hasGather = this->m_hasScatter = true;
@@ -1063,15 +1063,8 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic, boo
         // Create TargetMachine
         std::string triple = GetTripleString();
 
-#if ISPC_LLVM_VERSION <= ISPC_LLVM_3_8
         llvm::Reloc::Model relocModel = m_generatePIC ? llvm::Reloc::PIC_ :
             llvm::Reloc::Default;
-#else
-        llvm::Optional<llvm::Reloc::Model> relocModel;
-        if (m_generatePIC) {
-          relocModel = llvm::Reloc::PIC_;
-        }
-#endif
         std::string featuresString = m_attributes;
         llvm::TargetOptions options;
 #ifdef ISPC_ARM_ENABLED
@@ -1102,14 +1095,6 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic, boo
 #else /* LLVM 3.7+ */
         m_targetMachine->Options.MCOptions.AsmVerbose = true;
 #endif
-
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5
-        // Change default version of generated DWARF.
-        if (g->generateDWARFVersion != 0) {
-            m_targetMachine->Options.MCOptions.DwarfVersion = g->generateDWARFVersion;
-        }
-#endif
-
         // Initialize TargetData/DataLayout in 3 steps.
         // 1. Get default data layout first
         std::string dl_string;
@@ -1214,7 +1199,7 @@ Target::SupportedTargets() {
         "avx512skx-i32x16, "
 #endif
         "generic-x1, generic-x4, generic-x8, generic-x16, "
-        "generic-x32, generic-x64, *-generic-x16"
+        "generic-x32, generic-x64, *-generic-x16, "
 #ifdef ISPC_ARM_ENABLED
         ", neon-i8x16, neon-i16x8, neon-i32x4"
 #endif
@@ -1287,10 +1272,8 @@ Target::ISAToString(ISA isa) {
     case Target::KNL_AVX512:
         return "avx512knl";
 #endif
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
     case Target::SKX_AVX512:
         return "avx512skx";
-#endif
     case Target::GENERIC:
         return "generic";
 #ifdef ISPC_NVPTX_ENABLED
@@ -1527,9 +1510,6 @@ Globals::Globals() {
     emitPerfWarnings = true;
     emitInstrumentation = false;
     generateDebuggingSymbols = false;
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5
-    generateDWARFVersion = 0;
-#endif
     enableFuzzTest = false;
     fuzzTestSeed = -1;
     mangleFunctionsWithTarget = false;

ispc.h

@@ -606,16 +606,6 @@ struct Globals {
         program in its output. */
     bool generateDebuggingSymbols;
 
-    /** Require generation of DWARF of certain version (2, 3, 4). For
-        default version, this field is set to 0. */
-    // Hint: to verify dwarf version in the object file, run on Linux:
-    // readelf --debug-dump=info object.o | grep -A 2 'Compilation Unit @'
-    // on Mac:
-    // xcrun dwarfdump -r0 object.o
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5
-    int generateDWARFVersion;
-#endif
-
     /** If true, function names are mangled by appending the target ISA and
         vector width to them. */
     bool mangleFunctionsWithTarget;

ispc.vcxproj

@@ -38,8 +38,6 @@
     <ClCompile Include="$(Configuration)\gen-bitcode-avx2-i64x4-64bit.cpp" />
     <ClCompile Include="$(Configuration)\gen-bitcode-knl-32bit.cpp" />
     <ClCompile Include="$(Configuration)\gen-bitcode-knl-64bit.cpp" />
-    <ClCompile Include="$(Configuration)\gen-bitcode-skx-32bit.cpp" />
-    <ClCompile Include="$(Configuration)\gen-bitcode-skx-64bit.cpp" />
     <ClCompile Include="$(Configuration)\gen-bitcode-c-32.cpp" />
     <ClCompile Include="$(Configuration)\gen-bitcode-c-64.cpp" />
     <ClCompile Include="$(Configuration)\gen-bitcode-dispatch.cpp" />
@@ -293,16 +291,6 @@
       <Message>Building gen-bitcode-knl-32bit.cpp and gen-bitcode-knl-64bit.cpp</Message>
     </CustomBuild>
   </ItemGroup>
-  <ItemGroup>
-    <CustomBuild Include="builtins\target-skx.ll">
-      <FileType>Document</FileType>
-      <Command>m4 -Ibuiltins/ -DLLVM_VERSION=%LLVM_VERSION% -DBUILD_OS=WINDOWS -DRUNTIME=32 builtins/target-skx.ll | python bitcode2cpp.py builtins\target-skx.ll 32bit &gt; $(Configuration)/gen-bitcode-skx-32bit.cpp;
-               m4 -Ibuiltins/ -DLLVM_VERSION=%LLVM_VERSION% -DBUILD_OS=WINDOWS -DRUNTIME=64 builtins/target-skx.ll | python bitcode2cpp.py builtins\target-skx.ll 64bit &gt; $(Configuration)/gen-bitcode-skx-64bit.cpp</Command>
-      <Outputs>$(Configuration)/gen-bitcode-skx-32bit.cpp; $(Configuration)/gen-bitcode-skx-64bit.cpp</Outputs>
-      <AdditionalInputs>builtins\util.m4;builtins\svml.m4;builtins\target-avx-common.ll;builtins\target-avx.ll</AdditionalInputs>
-      <Message>Building gen-bitcode-skx-32bit.cpp and gen-bitcode-skx-64bit.cpp</Message>
-    </CustomBuild>
-  </ItemGroup>
   <ItemGroup>
     <CustomBuild Include="builtins\target-generic-1.ll">
       <FileType>Document</FileType>

ispc_version.h

@@ -38,7 +38,7 @@
 #ifndef ISPC_VERSION_H
 #define ISPC_VERSION_H
 
-#define ISPC_VERSION "1.9.1"
+#define ISPC_VERSION "1.9.1dev"
 #include "llvm/Config/llvm-config.h"
 
 #define ISPC_LLVM_VERSION ( LLVM_VERSION_MAJOR * 10000 + LLVM_VERSION_MINOR * 100 )

lex.ll

@@ -637,14 +637,14 @@ lParseInteger(bool dotdotdot) {
             // No u or l suffix
             // If we're compiling to an 8-bit mask target and the constant
             // fits into 8 bits, return an 8-bit int.
-            if (g->target->getDataTypeWidth() == 8) {
+            if (g->target->getMaskBitCount() == 8) {
                 if (yylval.intVal <= 0x7fULL)
                     return TOKEN_INT8_CONSTANT;
                 else if (yylval.intVal <= 0xffULL)
                     return TOKEN_UINT8_CONSTANT;
             }
             // And similarly for 16-bit masks and constants
-            if (g->target->getDataTypeWidth() == 16) {
+            if (g->target->getMaskBitCount() == 16) {
                 if (yylval.intVal <= 0x7fffULL)
                     return TOKEN_INT16_CONSTANT;
                 else if (yylval.intVal <= 0xffffULL)

main.cpp

@@ -103,16 +103,13 @@ usage(int ret) {
     printf("    [--dev-stub <filename>]\t\tEmit device-side offload stub functions to file\n");
 #ifdef ISPC_IS_WINDOWS
     printf("    [--dllexport]\t\t\tMake non-static functions DLL exported.  Windows only.\n");
-#endif
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5
-    printf("    [--dwarf-version={2,3,4}]\t\tGenerate source-level debug information with given DWARF version (triggers -g)\n");
 #endif
     printf("    [--emit-asm]\t\t\tGenerate assembly language file as output\n");
     printf("    [--emit-c++]\t\t\tEmit a C++ source file as output\n");
     printf("    [--emit-llvm]\t\t\tEmit LLVM bitode file as output\n");
     printf("    [--emit-obj]\t\t\tGenerate object file file as output (default)\n");
     printf("    [--force-alignment=<value>]\t\tForce alignment in memory allocations routine to be <value>\n");
-    printf("    [-g]\t\t\t\tGenerate source-level debug information\n");
+    printf("    [-g]\t\t\t\tGenerate debugging information\n");
     printf("    [--help]\t\t\t\tPrint help\n");
     printf("    [--help-dev]\t\t\tPrint help for developer options\n");
     printf("    [--host-stub <filename>]\t\tEmit host-side offload stub functions to file\n");
@@ -124,12 +121,12 @@ usage(int ret) {
     printf("        fast\t\t\t\tUse high-performance but lower-accuracy math functions\n");
     printf("        svml\t\t\t\tUse the Intel(r) SVML math libraries\n");
     printf("        system\t\t\t\tUse the system's math library (*may be quite slow*)\n");
-    printf("    [-MMM <filename>\t\t\tWrite #include dependencies to given file.\n");
+    printf("    [-MMM <filename>\t\t\t\tWrite #include dependencies to given file.\n");
     printf("    [--no-omit-frame-pointer]\t\tDisable frame pointer omission. It may be useful for profiling\n");
     printf("    [--nostdlib]\t\t\tDon't make the ispc standard library available\n");
     printf("    [--nocpp]\t\t\t\tDon't run the C preprocessor\n");
     printf("    [-o <name>/--outfile=<name>]\tOutput filename (may be \"-\" for standard output)\n");
-    printf("    [-O0/-O(1/2/3)]\t\t\tSet optimization level (off or on). Optimizations are on by default.\n");
+    printf("    [-O0/-O(1/2/3)]\t\t\t\tSet optimization level (off or on). Optimizations are on by default.\n");
     printf("    [--opt=<option>]\t\t\tSet optimization option\n");
     printf("        disable-assertions\t\tRemove assertion statements from final code.\n");
     printf("        disable-fma\t\t\tDisable 'fused multiply-add' instructions (on targets that support them)\n");
@@ -389,19 +386,6 @@ int main(int Argc, char *Argv[]) {
 #ifdef ISPC_IS_WINDOWS
         else if (!strcmp(argv[i], "--dllexport"))
             g->dllExport = true;
-#endif
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_5
-        else if (!strncmp(argv[i], "--dwarf-version=", 16)) {
-            int val = atoi(argv[i] + 16);
-            if (2 <= val && val <=4) {
-                g->generateDebuggingSymbols = true;
-                g->generateDWARFVersion=val;
-            } else {
-                fprintf(stderr, "Invalid value for DWARF version: \"%s\" -- "
-                        "only 2, 3 and 4 are allowed.\n", argv[i]+16);
-                usage(1);
-            }
-        }
 #endif
         else if (!strcmp(argv[i], "--print-target"))
             g->printTarget = true;

module.cpp

@@ -167,11 +167,6 @@ lDeclareSizeAndPtrIntTypes(SymbolTable *symbolTable) {
  */
 static void
 lStripUnusedDebugInfo(llvm::Module *module) {
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_9
-    // In LLVM 3.9 Global DCE is much more efficient than the LLVM 3.8's one.
-    // So, the fruitfulness of this function is negligible.
-    return;
-#else
     if (g->generateDebuggingSymbols == false)
         return;
 #if ISPC_LLVM_VERSION <= ISPC_LLVM_3_5 // <= 3.5
@@ -373,7 +368,6 @@ lStripUnusedDebugInfo(llvm::Module *module) {
     }
     for (int i = 0; i < (int)toErase.size(); ++i)
         module->eraseNamedMetadata(toErase[i]);
-#endif
 }