Revert "Fix for Revision 269218"

Fix for Revision 269218

LICENSE.txt

@@ -1,4 +1,4 @@
-Copyright (c) 2010-2015, Intel Corporation
+Copyright (c) 2010-2016, Intel Corporation
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without

Makefile

@@ -45,15 +45,15 @@ Location of LLVM files in your PATH is different than path in LLVM_HOME \n
 variable (or LLVM_HOME is not set). The most likely this means that you are \n
 using default LLVM installation on your system, which is very bad sign. \n
 Note, that ISPC uses LLVM optimizer and is highly dependent on it. We recommend \n
-using *patched* version of LLVM 3.4 or 3.5. Patches are availible in \n
+using *patched* version of LLVM 3.8. Patches are availible in \n
 llvm_patches folder. You can build LLVM manually, or run our scripts, which \n
 will do all the work for you. Do the following: \n
 1. Create a folder, where LLVM will reside and set LLVM_HOME variable to its \n
   path. \n
 2. Set ISPC_HOME variable to your ISPC location (probably current folder).
 3. Run alloy.py tool to checkout and build LLVM: \n
-  alloy.py -b --version=3.5 \n
+  alloy.py -b --version=3.8 \n
-4. Add $$LLVM_HOME/bin-3.5/bin path to your PATH. \n
+4. Add $$LLVM_HOME/bin-3.8/bin path to your PATH. \n
 ==============================================================================
 endef
 
@@ -202,7 +202,7 @@ HEADERS=ast.h builtins.h ctx.h decl.h expr.h func.h ispc.h llvmutil.h module.h \
 	opt.h stmt.h sym.h type.h util.h
 TARGETS=avx2-i64x4 avx11-i64x4 avx1-i64x4 avx1 avx1-x2 avx11 avx11-x2 avx2 avx2-x2 \
 	sse2 sse2-x2 sse4-8 sse4-16 sse4 sse4-x2 \
-	generic-4 generic-8 generic-16 generic-32 generic-64 generic-1 knl
+	generic-4 generic-8 generic-16 generic-32 generic-64 generic-1 knl skx
 ifneq ($(ARM_ENABLED), 0)
     TARGETS+=neon-32 neon-16 neon-8
 endif

alloy.py

@@ -125,7 +125,7 @@ def build_LLVM(version_LLVM, revision, folder, tarball, debug, selfbuild, extra,
     if  version_LLVM == "trunk":
         SVN_PATH="trunk"
     if  version_LLVM == "3.8":
-        SVN_PATH="branches/release_38"
+        SVN_PATH="tags/RELEASE_380/final"
         version_LLVM = "3_8"
     if  version_LLVM == "3.7":
         SVN_PATH="tags/RELEASE_370/final"
@@ -241,13 +241,14 @@ def build_LLVM(version_LLVM, revision, folder, tarball, debug, selfbuild, extra,
     os.makedirs(LLVM_BUILD)
     os.makedirs(LLVM_BIN)
     selfbuild_compiler = ""
+    LLVM_configure_capable = ["3_2", "3_3", "3_4", "3_5", "3_6", "3_7"]
     if selfbuild:
         print_debug("Making selfbuild and use folders " + LLVM_BUILD_selfbuild + " and " +
             LLVM_BIN_selfbuild + "\n", from_validation, alloy_build)
         os.makedirs(LLVM_BUILD_selfbuild)
         os.makedirs(LLVM_BIN_selfbuild)
         os.chdir(LLVM_BUILD_selfbuild)
-        if  version_LLVM == "trunk":
+        if  version_LLVM not in LLVM_configure_capable:
             # TODO: mac_root
             try_do_LLVM("configure release version for selfbuild ",
                     "cmake -G Unix\ Makefiles" + " -DCMAKE_EXPORT_COMPILE_COMMANDS=ON" +
@@ -283,7 +284,7 @@ def build_LLVM(version_LLVM, revision, folder, tarball, debug, selfbuild, extra,
     os.chdir(LLVM_BUILD)
     if debug == False:
         if current_OS != "Windows":
-            if  version_LLVM == "trunk":
+            if  version_LLVM not in LLVM_configure_capable:
                 # TODO: mac_root
                 try_do_LLVM("configure release version ",
                         "cmake -G Unix\ Makefiles" + " -DCMAKE_EXPORT_COMPILE_COMMANDS=ON" +
@@ -311,7 +312,7 @@ def build_LLVM(version_LLVM, revision, folder, tarball, debug, selfbuild, extra,
                     '" -DLLVM_LIT_TOOLS_DIR="C:\\gnuwin32\\bin" ..\\' + LLVM_SRC,
                     from_validation)
     else:
-        if  version_LLVM == "trunk":
+        if  version_LLVM not in LLVM_configure_capable:
             # TODO: mac_root
             try_do_LLVM("configure debug version ",
                     "cmake -G Unix\ Makefiles" + " -DCMAKE_EXPORT_COMPILE_COMMANDS=ON" +
@@ -343,12 +344,12 @@ def build_LLVM(version_LLVM, revision, folder, tarball, debug, selfbuild, extra,
 
 
 def unsupported_llvm_targets(LLVM_VERSION):
-    prohibited_list = {"3.2":["avx512knl-i32x16"],
+    prohibited_list = {"3.2":["avx512knl-i32x16", "avx512skx-i32x16"],
-                       "3.3":["avx512knl-i32x16"],
+                       "3.3":["avx512knl-i32x16", "avx512skx-i32x16"],
-                       "3.4":["avx512knl-i32x16"],
+                       "3.4":["avx512knl-i32x16", "avx512skx-i32x16"],
-                       "3.5":["avx512knl-i32x16"],
+                       "3.5":["avx512knl-i32x16", "avx512skx-i32x16"],
-                       "3.6":["avx512knl-i32x16"],
+                       "3.6":["avx512knl-i32x16", "avx512skx-i32x16"],
-                       "3.7":[],
+                       "3.7":["avx512skx-i32x16"],
                        "3.8":[],
                        "3.9":[],
                        "trunk":[]}   
@@ -377,9 +378,10 @@ def check_targets():
     AVX11 = ["avx1.1-i32x8","avx1.1-i32x16","avx1.1-i64x4"]
     AVX2  = ["avx2-i32x8",  "avx2-i32x16",  "avx2-i64x4"]
     KNL   = ["knl-generic", "avx512knl-i32x16"]
+    SKX   = ["avx512skx-i32x16"]
 
     targets = [["AVX2", AVX2, False], ["AVX1.1", AVX11, False], ["AVX", AVX, False], ["SSE4", SSE4, False], 
-               ["SSE2", SSE2, False], ["KNL", KNL, False]]
+               ["SSE2", SSE2, False], ["KNL", KNL, False], ["SKX", SKX, False]]
     f_lines = take_lines("check_isa.exe", "first")
     for i in range(0,5):
         if targets[i][0] in f_lines:
@@ -403,6 +405,8 @@ def check_targets():
     # here we have SDE
     f_lines = take_lines(sde_exists + " -help", "all")
     for i in range(0,len(f_lines)):
+        if targets[6][2] == False and "skx" in f_lines[i]:
+            answer_sde = answer_sde + [["-skx", "avx512skx-i32x16"]]
         if targets[5][2] == False and "knl" in f_lines[i]:
             answer_sde = answer_sde + [["-knl", "knl-generic"], ["-knl", "avx512knl-i32x16"]]
         if targets[3][2] == False and "wsm" in f_lines[i]:
@@ -727,7 +731,10 @@ def validation_run(only, only_targets, reference_branch, number, notify, update,
                 # *always* specify default values for global variables on each loop iteration
                 stability.wrapexe = ""
                 stability.compiler_exe = None
-
+                # choosing right compiler for a given target
+                # sometimes clang++ is not avaluable. if --ispc-build-compiler = gcc we will pass in g++ compiler
+                if options.ispc_build_compiler == "gcc":
+                    stability.compiler_exe = "g++"
                 if ("knc-generic" in stability.target) or ("knl-generic" in stability.target):
                     stability.compiler_exe = "icpc"
                 stability.wrapexe = get_sde() + " " + sde_targets[j][0] + " -- "

builtins.cpp

@@ -1377,6 +1377,23 @@ DefineStdlib(SymbolTable *symbolTable, llvm::LLVMContext *ctx, llvm::Module *mod
         }
         break;
     }
+#endif
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+    case Target::SKX_AVX512: {
+        switch (g->target->getVectorWidth()) {
+        case 16:
+            if (runtime32) {
+                EXPORT_MODULE(builtins_bitcode_skx_32bit);
+            }
+            else {
+                EXPORT_MODULE(builtins_bitcode_skx_64bit);
+            }
+            break;
+        default:
+            FATAL("logic error in DefineStdlib");
+        }
+        break;
+    }
 #endif
     case Target::GENERIC: {
         switch (g->target->getVectorWidth()) {

builtins/target-avx512-common.ll

@@ -511,13 +511,6 @@ define float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
   ret float %half_scale
 }
 
-declare <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
-
-define <16 x float> @__rsqrt_varying_float(<16 x float> %v) nounwind readonly alwaysinline {
-  %res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float> %v, <16 x float> undef, i16 -1, i32 8)
-  ret <16 x float> %res  
-}
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; rcp
 
@@ -538,13 +531,6 @@ define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
   ret float %iv_mul
 }
 
-declare <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
-
-define <16 x float> @__rcp_varying_float(<16 x float>) nounwind readonly alwaysinline {
-  %res = call <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float> %0, <16 x float> undef, i16 -1, i32 8)
-  ret <16 x float> %res
-}
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; sqrt
 

builtins/target-knl.ll

@@ -31,7 +31,6 @@
 
 define(`WIDTH',`16')
 
-
 ifelse(LLVM_VERSION, LLVM_3_7,
     `include(`target-avx512-common.ll')',
          LLVM_VERSION, LLVM_3_8,
@@ -40,5 +39,28 @@ ifelse(LLVM_VERSION, LLVM_3_7,
     `include(`target-avx512-common.ll')'
   )
 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; rcp, rsqrt
+
+define(`rcp_rsqrt_varying_float_knl',`
+declare <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
+define <16 x float> @__rcp_varying_float(<16 x float>) nounwind readonly alwaysinline {
+  %res = call <16 x float> @llvm.x86.avx512.rcp28.ps(<16 x float> %0, <16 x float> undef, i16 -1, i32 8)
+  ret <16 x float> %res
+}
+declare <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float>, <16 x float>, i16, i32) nounwind readnone
+define <16 x float> @__rsqrt_varying_float(<16 x float> %v) nounwind readonly alwaysinline {
+  %res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps(<16 x float> %v, <16 x float> undef, i16 -1, i32 8)
+  ret <16 x float> %res
+}
+')
+
+ifelse(LLVM_VERSION, LLVM_3_7,
+    rcp_rsqrt_varying_float_knl(),
+         LLVM_VERSION, LLVM_3_8,
+    rcp_rsqrt_varying_float_knl(),
+         LLVM_VERSION, LLVM_3_9,
+    rcp_rsqrt_varying_float_knl()
+  )
 
 ;;saturation_arithmetic_novec()

builtins/target-skx.ll

@@ -0,0 +1,86 @@
+;;  Copyright (c) 2016, Intel Corporation
+;;  All rights reserved.
+;;
+;;  Redistribution and use in source and binary forms, with or without
+;;  modification, are permitted provided that the following conditions are
+;;  met:
+;;
+;;    * Redistributions of source code must retain the above copyright
+;;      notice, this list of conditions and the following disclaimer.
+;;
+;;    * Redistributions in binary form must reproduce the above copyright
+;;      notice, this list of conditions and the following disclaimer in the
+;;      documentation and/or other materials provided with the distribution.
+;;
+;;    * Neither the name of Intel Corporation nor the names of its
+;;      contributors may be used to endorse or promote products derived from
+;;      this software without specific prior written permission.
+;;
+;;
+;;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+;;   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+;;   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+;;   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+;;   OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+;;   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+;;   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;;   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+;;   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+;;   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+;;   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+define(`WIDTH',`16')
+
+
+ifelse(LLVM_VERSION, LLVM_3_8,
+    `include(`target-avx512-common.ll')',
+         LLVM_VERSION, LLVM_3_9,
+    `include(`target-avx512-common.ll')'
+  )
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; rcp, rsqrt
+
+define(`rcp_rsqrt_varying_float_skx',`
+declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>, <16 x float>, i16) nounwind readnone
+define <16 x float> @__rcp_varying_float(<16 x float>) nounwind readonly alwaysinline {
+  %call = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> %0, <16 x float> undef, i16 -1)
+  ;; do one Newton-Raphson iteration to improve precision
+  ;;  float iv = __rcp_v(v);
+  ;;  return iv * (2. - v * iv);
+  %v_iv = fmul <16 x float> %0`,' %call
+  %two_minus = fsub <16 x float> <float 2.`,' float 2.`,' float 2.`,' float 2.`,'
+                                  float 2.`,' float 2.`,' float 2.`,' float 2.`,'
+                                  float 2.`,' float 2.`,' float 2.`,' float 2.`,'
+                                  float 2.`,' float 2.`,' float 2.`,' float 2.>`,' %v_iv
+  %iv_mul = fmul <16 x float> %call`,'  %two_minus
+  ret <16 x float> %iv_mul
+}
+declare <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float>`,'  <16 x float>`,'  i16) nounwind readnone
+define <16 x float> @__rsqrt_varying_float(<16 x float> %v) nounwind readonly alwaysinline {
+  %is = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> %v`,'  <16 x float> undef`,'  i16 -1)
+  ; Newton-Raphson iteration to improve precision
+  ;  float is = __rsqrt_v(v);
+  ;  return 0.5 * is * (3. - (v * is) * is);
+  %v_is = fmul <16 x float> %v`,'  %is
+  %v_is_is = fmul <16 x float> %v_is`,'  %is
+  %three_sub = fsub <16 x float> <float 3.`,' float 3.`,' float 3.`,' float 3.`,'
+                                  float 3.`,' float 3.`,' float 3.`,' float 3.`,'
+                                  float 3.`,' float 3.`,' float 3.`,' float 3.`,'
+                                  float 3.`,' float 3.`,' float 3.`,' float 3.>`,' %v_is_is
+  %is_mul = fmul <16 x float> %is`,'  %three_sub
+  %half_scale = fmul <16 x float> <float 0.5`,' float 0.5`,' float 0.5`,' float 0.5`,'
+                                   float 0.5`,' float 0.5`,' float 0.5`,' float 0.5`,'
+                                   float 0.5`,' float 0.5`,' float 0.5`,' float 0.5`,'
+                                   float 0.5`,' float 0.5`,' float 0.5`,' float 0.5>`,' %is_mul
+  ret <16 x float> %half_scale
+}
+')
+
+ifelse(LLVM_VERSION, LLVM_3_8,
+    rcp_rsqrt_varying_float_skx(),
+         LLVM_VERSION, LLVM_3_9,
+    rcp_rsqrt_varying_float_skx()
+  )
+
+;;saturation_arithmetic_novec()

cbackend.cpp

@@ -1641,7 +1641,7 @@ void CWriter::printConstant(llvm::Constant *CPV, bool Static) {
         V = Tmp.convertToDouble();
       }
 
-      if (isnan(V)) {
+      if (std::isnan(V)) {
         // The value is NaN
 
         // FIXME the actual NaN bits should be emitted.
@@ -1665,7 +1665,7 @@ void CWriter::printConstant(llvm::Constant *CPV, bool Static) {
         else
           Out << "LLVM_NAN" << (Val == QuietNaN ? "" : "S") << "(\""
               << Buffer << "\") /*nan*/ ";
-      } else if (isinf(V)) {
+      } else if (std::isinf(V)) {
         // The value is Inf
         if (V < 0) Out << '-';
         Out << "LLVM_INF" <<
@@ -3343,7 +3343,11 @@ void CWriter::printFunction(llvm::Function &F) {
   // print the basic blocks
   for (llvm::Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
     if (llvm::Loop *L = LI->getLoopFor(&*BB)) {
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_9 // LLVM 3.9+
+      if (L->getHeader()->getIterator() == BB && L->getParentLoop() == 0)
+#else
       if (L->getHeader() == BB && L->getParentLoop() == 0)
+#endif
         printLoop(L);
     } else {
       printBasicBlock(&*BB);

contrib/ispc.vim

@@ -1,7 +1,7 @@
 " Vim syntax file
 " Language:	ISPC
 " Maintainer:	Andreas Wendleder <andreas.wendleder@gmail.com>
-" Last Change:	2011 Aug 3
+" Last Change:	2016 May 04
 
 " Quit when a syntax file was already loaded
 if exists("b:current_syntax")
@@ -13,11 +13,11 @@ runtime! syntax/c.vim
 unlet b:current_syntax
 
 " New keywords
-syn keyword	ispcStatement	cbreak ccontinue creturn launch print reference soa sync task
+syn keyword	ispcStatement	cbreak ccontinue creturn launch print reference soa sync
 syn keyword	ispcConditional	cif
-syn keyword	ispcRepeat	cdo cfor cwhile
+syn keyword	ispcRepeat	cdo cfor cwhile foreach foreach_tiled foreach_unique foreach_active
-syn keyword	ispcBuiltin	programCount programIndex	
+syn keyword	ispcBuiltin	programCount programIndex taskCount taskCount0 taskCount1 taskCount3 taskIndex taskIndex0 taskIndex1 taskIndex2
-syn keyword	ispcType	export uniform varying int8 int16 int32 int64
+syn keyword	ispcType	export uniform varying int8 int16 int32 int64 task new delete
 syn keyword	ispcOperator	operator
 
 "double precision floating point number, with dot, optional exponent

doxygen.cfg

@@ -31,7 +31,7 @@ PROJECT_NAME           = "Intel SPMD Program Compiler"
 # This could be handy for archiving the generated documentation or
 # if some version control system is used.
 
-PROJECT_NUMBER         = 1.9.0
+PROJECT_NUMBER         = 1.9.1dev
 
 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
 # base path where the generated documentation will be put.

examples/aobench/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=ao
 CPP_SRC=ao.cpp ao_serial.cpp
 ISPC_SRC=ao.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x4,avx1-i32x8,avx2-i32x8
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x4,avx1-i32x8,avx2-i32x8,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/common.mk

@@ -35,6 +35,12 @@ ifeq ($(ARCH),x86)
     ifneq (,$(findstring avx2,$(ISPC_IA_TARGETS)))
       ISPC_OBJS+=$(addprefix objs/, $(ISPC_SRC:.ispc=)_ispc_avx2.o)
     endif
+    ifneq (,$(findstring avx512knl,$(ISPC_IA_TARGETS)))
+      ISPC_OBJS+=$(addprefix objs/, $(ISPC_SRC:.ispc=)_ispc_avx512knl.o)
+    endif
+    ifneq (,$(findstring avx512skx,$(ISPC_IA_TARGETS)))
+      ISPC_OBJS+=$(addprefix objs/, $(ISPC_SRC:.ispc=)_ispc_avx512skx.o)
+    endif
   endif
   ISPC_TARGETS=$(ISPC_IA_TARGETS)
   ARCH_BIT:=$(shell getconf LONG_BIT)
@@ -86,7 +92,7 @@ objs/%.o: ../%.cpp dirs
 
 objs/$(EXAMPLE).o: objs/$(EXAMPLE)_ispc.h dirs
 
-objs/%_ispc.h objs/%_ispc.o objs/%_ispc_sse2.o objs/%_ispc_sse4.o objs/%_ispc_avx.o objs/%_ispc_avx11.o objs/%_ispc_avx2.o: %.ispc dirs
+objs/%_ispc.h objs/%_ispc.o objs/%_ispc_sse2.o objs/%_ispc_sse4.o objs/%_ispc_avx.o objs/%_ispc_avx11.o objs/%_ispc_avx2.o objs/%_ispc_avx512knl.o objs/%_ispc_avx512skx.o : %.ispc dirs
 	$(ISPC) $(ISPC_FLAGS) --target=$(ISPC_TARGETS) $< -o objs/$*_ispc.o -h objs/$*_ispc.h
 
 objs/$(ISPC_SRC:.ispc=)_sse4.cpp: $(ISPC_SRC)

examples/deferred/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=deferred_shading
 CPP_SRC=common.cpp main.cpp dynamic_c.cpp dynamic_cilk.cpp
 ISPC_SRC=kernels.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 ISPC_FLAGS=--opt=fast-math
 

examples/gmres/Makefile

@@ -3,7 +3,7 @@ EXAMPLE=gmres
 CPP_SRC=algorithm.cpp main.cpp matrix.cpp
 CC_SRC=mmio.c
 ISPC_SRC=matrix.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/mandelbrot/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=mandelbrot
 CPP_SRC=mandelbrot.cpp mandelbrot_serial.cpp
 ISPC_SRC=mandelbrot.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/mandelbrot_tasks/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=mandelbrot_tasks
 CPP_SRC=mandelbrot_tasks.cpp mandelbrot_tasks_serial.cpp
 ISPC_SRC=mandelbrot_tasks.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/noise/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=noise
 CPP_SRC=noise.cpp noise_serial.cpp
 ISPC_SRC=noise.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x4,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x4,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/options/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=options
 CPP_SRC=options.cpp options_serial.cpp
 ISPC_SRC=options.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/perfbench/Makefile

@@ -1,5 +1,5 @@
 
-EXAMPLE=perbench
+EXAMPLE=perfbench
 CPP_SRC=perfbench.cpp perfbench_serial.cpp
 ISPC_SRC=perfbench.ispc
 ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x4,avx1-i32x8,avx2-i32x8

examples/rt/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=rt
 CPP_SRC=rt.cpp rt_serial.cpp
 ISPC_SRC=rt.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x8,avx2-i32x8
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x8,avx2-i32x8,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/sort/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=sort
 CPP_SRC=sort.cpp sort_serial.cpp
 ISPC_SRC=sort.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x8,avx2-i32x8
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x8,avx2-i32x8,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 #ISPC_FLAGS=-DDEBUG
 

examples/stencil/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=stencil
 CPP_SRC=stencil.cpp stencil_serial.cpp
 ISPC_SRC=stencil.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x16,avx2-i32x16,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

examples/volume_rendering/Makefile

@@ -2,7 +2,7 @@
 EXAMPLE=volume
 CPP_SRC=volume.cpp volume_serial.cpp
 ISPC_SRC=volume.ispc
-ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x8,avx2-i32x8
+ISPC_IA_TARGETS=sse2-i32x4,sse4-i32x8,avx1-i32x8,avx2-i32x8,avx512knl-i32x16,avx512skx-i32x16
 ISPC_ARM_TARGETS=neon
 
 include ../common.mk

fail_db.txt

@@ -121,6 +121,8 @@
 ./tests/test-143.ispc runfail  x86-64     generic-16   Linux LLVM 3.7 clang++3.4 -O0 *
 ./tests/test-143.ispc runfail  x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O2 *
 ./tests/test-143.ispc runfail  x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O0 *
+./tests/test-143.ispc runfail  x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/test-143.ispc runfail  x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
 ./tests/masked-scatter-struct.ispc runfail  x86-64      generic-4   Linux LLVM 3.5 clang++3.4 -O2 *
 ./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.5 clang++3.4 -O2 *
 ./tests/ptr-15.ispc runfail  x86-64      generic-4   Linux LLVM 3.3 clang++3.4 -O0 *
@@ -135,6 +137,8 @@
 ./tests/ptr-15.ispc runfail  x86-64     generic-16   Linux LLVM 3.7 clang++3.4 -O0 *
 ./tests/ptr-15.ispc runfail  x86-64      generic-4   Linux LLVM 3.8 clang++3.4 -O0 *
 ./tests/ptr-15.ispc runfail  x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O0 *
+./tests/ptr-15.ispc runfail  x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/ptr-15.ispc runfail  x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
 ./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.5 clang++3.4 -O0 *
 .\tests\foreach-double-1.ispc runfail     x86     avx2-i32x8 Windows LLVM 3.5         cl -O2 *
 .\tests\foreach-double-1.ispc runfail     x86    avx2-i32x16 Windows LLVM 3.5         cl -O2 *
@@ -151,6 +155,8 @@
 ./tests/ptr-22.ispc runfail  x86-64     generic-16   Linux LLVM 3.7 clang++3.4 -O0 *
 ./tests/ptr-22.ispc runfail  x86-64      generic-4   Linux LLVM 3.8 clang++3.4 -O0 *
 ./tests/ptr-22.ispc runfail  x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O0 *
+./tests/ptr-22.ispc runfail  x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/ptr-22.ispc runfail  x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
 ./tests/masked-scatter-struct.ispc runfail  x86-64      generic-4   Linux LLVM 3.6 clang++3.4 -O2 *
 ./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.6 clang++3.4 -O2 *
 ./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.6 clang++3.4 -O0 *
@@ -160,10 +166,15 @@
 ./tests/ptr-19.ispc runfail  x86-64     generic-16   Linux LLVM 3.6 clang++3.4 -O0 *
 ./tests/ptr-19.ispc runfail  x86-64     generic-16   Linux LLVM 3.7 clang++3.4 -O0 *
 ./tests/ptr-19.ispc runfail  x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O0 *
+./tests/ptr-19.ispc runfail  x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
 ./tests/masked-scatter-struct.ispc runfail  x86-64      generic-4   Linux LLVM 3.7 clang++3.4 -O2 *
 ./tests/masked-scatter-struct.ispc runfail  x86-64      generic-4   Linux LLVM 3.8 clang++3.4 -O2 *
 ./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.7 clang++3.4 -O2 *
 ./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.7 clang++3.4 -O0 *
+./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.8 clang++3.4 -O2 *
+./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.8 clang++3.4 -O0 *
+./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/short-vec-8.ispc compfail  x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
 
 % [KNC-generic]: vec16-i64 memory layout bugs. Need to rewrite knc.h to fix that
 ./tests/soa-18.ispc runfail  x86-64 knc-generic   Linux LLVM 3.4   icpc13.1 -O0 *
@@ -379,4 +390,36 @@
 ./tests/short-vec-7.ispc compfail     x86-64      generic-4   Linux LLVM 3.8 clang++3.4 -O2 *
 ./tests/short-vec-7.ispc compfail     x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O0 *
 ./tests/short-vec-7.ispc compfail     x86-64     generic-16   Linux LLVM 3.8 clang++3.4 -O2 *
+./tests/pointer-decl-craziness-1.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/pointer-decl-craziness-1.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/pointer-decl-craziness-1.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/pointer-decl-craziness-1.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/pointer-decl-craziness-3.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/pointer-decl-craziness-3.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/pointer-decl-craziness-3.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/pointer-decl-craziness-3.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/pointer-decl-craziness.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/pointer-decl-craziness.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/pointer-decl-craziness.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/pointer-decl-craziness.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/ptr-23.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/ptr-23.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/ptr-23.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/ptr-23.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/ref-6.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/ref-6.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/ref-6.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/ref-6.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/scatter-vector.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/scatter-vector.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/scatter-vector.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/scatter-vector.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/short-vec-6.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/short-vec-6.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/short-vec-6.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/short-vec-6.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/short-vec-7.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/short-vec-7.ispc compfail     x86-64      generic-4   Linux LLVM 3.9 clang++3.4 -O2 *
+./tests/short-vec-7.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O0 *
+./tests/short-vec-7.ispc compfail     x86-64     generic-16   Linux LLVM 3.9 clang++3.4 -O2 *
 % End of anonymous namespace bug

ispc.cpp

@@ -165,7 +165,7 @@ lGetSystemISA() {
             (info2[1] & (1 << 28)) != 0 && // AVX512 CDI
             (info2[1] & (1 << 30)) != 0 && // AVX512 BW
             (info2[1] & (1 << 31)) != 0) { // AVX512 VL
-            return "skx";
+            return "avx512skx-i32x16";
         }
         else if ((info2[1] & (1 << 26)) != 0 && // AVX512 PF
                  (info2[1] & (1 << 27)) != 0 && // AVX512 ER
@@ -239,10 +239,24 @@ typedef enum {
 #endif
 
 #if ISPC_LLVM_VERSION >= ISPC_LLVM_3_7 // LLVM 3.7+
-    // KNL. Supports AVX512.
+    // Knights Landing - Xeon Phi.
+    // Supports AVX-512F: All the key AVX-512 features: masking, broadcast... ;
+    //          AVX-512CDI: Conflict Detection;
+    //          AVX-512ERI & PRI: 28-bit precision RCP, RSQRT and EXP transcendentals,
+    //                            new prefetch instructions.
     CPU_KNL,
 #endif
 
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+    // Skylake Xeon.
+    // Supports AVX-512F: All the key AVX-512 features: masking, broadcast... ;
+    //          AVX-512CDI: Conflict Detection;
+    //          AVX-512VL: Vector Length Orthogonality;
+    //          AVX-512DQ: New HPC ISA (vs AVX512F);
+    //          AVX-512BW: Byte and Word Support.
+    CPU_SKX,
+#endif
+
 #if ISPC_LLVM_VERSION >= ISPC_LLVM_3_4 // LLVM 3.4+
     // Late Atom-like design. Supports SSE 4.2 + POPCNT/LZCNT.
     CPU_Silvermont,
@@ -273,14 +287,14 @@ private:
     std::vector<std::vector<std::string> > names;
     std::vector<std::set<CPUtype> > compat;
 
-    std::set<CPUtype> Set(CPUtype type, ...) {
+    std::set<CPUtype> Set(int type, ...) {
         std::set<CPUtype> retn;
         va_list args;
 
-        retn.insert(type);
+        retn.insert((CPUtype)type);
         va_start(args, type);
-        while ((type = (CPUtype)va_arg(args, int)) != CPU_None)
+        while ((type = va_arg(args, int)) != CPU_None)
-            retn.insert(type);
+            retn.insert((CPUtype)type);
         va_end(args);
 
         return retn;
@@ -327,6 +341,10 @@ public:
          names[CPU_KNL].push_back("knl");
 #endif
 
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+         names[CPU_SKX].push_back("skx");
+#endif
+
 #ifdef ISPC_ARM_ENABLED
         names[CPU_CortexA15].push_back("cortex-a15");
 
@@ -353,6 +371,13 @@ public:
                                       CPU_Haswell, CPU_Broadwell, CPU_None);
 #endif
 
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+        compat[CPU_SKX]         = Set(CPU_SKX, CPU_Bonnell, CPU_Penryn,
+                                      CPU_Core2, CPU_Nehalem, CPU_Silvermont,
+                                      CPU_SandyBridge, CPU_IvyBridge,
+                                      CPU_Haswell, CPU_Broadwell, CPU_None);
+#endif
+
 #if ISPC_LLVM_VERSION <= ISPC_LLVM_3_5 // LLVM 3.2, 3.3, 3.4 or 3.5
         #define CPU_Broadwell CPU_Haswell
 #else /* LLVM 3.6+ */
@@ -513,6 +538,12 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic, boo
                 break;
 #endif
 
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+            case CPU_SKX:
+                isa = "avx512skx-i32x16";
+                break;
+#endif
+
 #if ISPC_LLVM_VERSION >= ISPC_LLVM_3_6
             case CPU_Broadwell:
 #endif
@@ -915,7 +946,26 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic, boo
         CPUfromISA = CPU_KNL;
     }
 #endif
-
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+    else if (!strcasecmp(isa, "avx512skx-i32x16")) {
+        this->m_isa = Target::SKX_AVX512;
+        this->m_nativeVectorWidth = 16;
+        this->m_nativeVectorAlignment = 64;
+        // ?? this->m_dataTypeWidth = 32;
+        this->m_vectorWidth = 16;
+        this->m_maskingIsFree = true;
+        this->m_maskBitCount = 1;
+        this->m_hasHalf = true;
+        this->m_hasRand = true;
+        this->m_hasGather = this->m_hasScatter = true;
+        this->m_hasTranscendentals = false;
+        // For MIC it is set to true due to performance reasons. The option should be tested.
+        this->m_hasTrigonometry = false;
+        this->m_hasRsqrtd = this->m_hasRcpd = false;
+        this->m_hasVecPrefetch = false;
+        CPUfromISA = CPU_SKX;
+    }
+#endif
 #ifdef ISPC_ARM_ENABLED
     else if (!strcasecmp(isa, "neon-i8x16")) {
         this->m_isa = Target::NEON8;
@@ -1144,6 +1194,9 @@ Target::SupportedTargets() {
         "avx2-i32x8, avx2-i32x16, avx2-i64x4, "
 #if ISPC_LLVM_VERSION >= ISPC_LLVM_3_7 // LLVM 3.7+
         "avx512knl-i32x16, "
+#endif
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
+        "avx512skx-i32x16, "
 #endif
         "generic-x1, generic-x4, generic-x8, generic-x16, "
         "generic-x32, generic-x64, *-generic-x16, "
@@ -1219,8 +1272,8 @@ Target::ISAToString(ISA isa) {
     case Target::KNL_AVX512:
         return "avx512knl";
 #endif
-    case Target::SKX:
+    case Target::SKX_AVX512:
-        return "skx";
+        return "avx512skx";
     case Target::GENERIC:
         return "generic";
 #ifdef ISPC_NVPTX_ENABLED
@@ -1267,8 +1320,10 @@ Target::ISAToTargetString(ISA isa) {
     case Target::KNL_AVX512:
         return "avx512knl-i32x16";
 #endif
-    case Target::SKX:
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // LLVM 3.8+
-        return "avx2";
+    case Target::SKX_AVX512:
+        return "avx512skx-i32x16";
+#endif
     case Target::GENERIC:
         return "generic-4";
 #ifdef ISPC_NVPTX_ENABLED

ispc.h

@@ -193,7 +193,7 @@ public:
         AVX11          = 3,
         AVX2           = 4,
         KNL_AVX512     = 5,
-        SKX            = 6,
+        SKX_AVX512     = 6,
         GENERIC        = 7,
 #ifdef ISPC_NVPTX_ENABLED
         NVPTX,

ispc_version.h

@@ -38,7 +38,7 @@
 #ifndef ISPC_VERSION_H
 #define ISPC_VERSION_H
 
-#define ISPC_VERSION "1.9.0"
+#define ISPC_VERSION "1.9.1dev"
 #include "llvm/Config/llvm-config.h"
 
 #define ISPC_LLVM_VERSION ( LLVM_VERSION_MAJOR * 10000 + LLVM_VERSION_MINOR * 100 )

llvm_patches/3_8_skx_patch_pack.patch

@@ -0,0 +1,248 @@
+--- lib/Target/X86/X86ISelLowering.cpp	2016-04-07 01:11:55.018960678 +0300
++++ lib/Target/X86/X86ISelLowering.cpp	2016-04-07 01:13:57.643965706 +0300
+@@ -1413,9 +1413,6 @@
+     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8i1,  Custom);
+     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v16i1, Custom);
+     if (Subtarget->hasDQI()) {
+-      setOperationAction(ISD::TRUNCATE,         MVT::v2i1, Custom);
+-      setOperationAction(ISD::TRUNCATE,         MVT::v4i1, Custom);
+-
+       setOperationAction(ISD::SINT_TO_FP,       MVT::v8i64, Legal);
+       setOperationAction(ISD::UINT_TO_FP,       MVT::v8i64, Legal);
+       setOperationAction(ISD::FP_TO_SINT,       MVT::v8i64, Legal);
+@@ -1709,6 +1706,8 @@
+     addRegisterClass(MVT::v4i1,   &X86::VK4RegClass);
+     addRegisterClass(MVT::v2i1,   &X86::VK2RegClass);
+ 
++    setOperationAction(ISD::TRUNCATE,           MVT::v2i1, Custom);
++    setOperationAction(ISD::TRUNCATE,           MVT::v4i1, Custom);
+     setOperationAction(ISD::SETCC,              MVT::v4i1, Custom);
+     setOperationAction(ISD::SETCC,              MVT::v2i1, Custom);
+     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v4i1, Custom);
+@@ -11737,10 +11736,15 @@
+   }
+ 
+   unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+-  const TargetRegisterClass* rc = getRegClassFor(VecVT);
+-  if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
+-    rc = getRegClassFor(MVT::v16i1);
+-  unsigned MaxSift = rc->getSize()*8 - 1;
++  if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8)) {
++    // Use kshiftlw/rw instruction.
++    VecVT = MVT::v16i1;
++    Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT,
++                      DAG.getUNDEF(VecVT),
++                      Vec,
++                      DAG.getIntPtrConstant(0, dl));
++  }
++  unsigned MaxSift = VecVT.getVectorNumElements() - 1;
+   Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
+                     DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
+   Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
+--- lib/Target/X86/X86InstrAVX512.td	2016-04-07 01:11:55.020960678 +0300
++++ lib/Target/X86/X86InstrAVX512.td	2016-04-07 01:12:30.680962140 +0300
+@@ -2043,9 +2043,6 @@
+                VEX, PD, VEX_W;
+   defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
+                VEX, XD;
+-}
+-
+-let Predicates = [HasBWI] in {
+   defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
+                VEX, PS, VEX_W;
+   defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
+@@ -2085,8 +2082,27 @@
+             (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
+   def : Pat<(store VK2:$src, addr:$dst),
+             (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
++  def : Pat<(store VK1:$src, addr:$dst),
++            (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
+ }
+ let Predicates = [HasAVX512, NoDQI] in {
++  def : Pat<(store VK1:$src, addr:$dst),
++            (MOV8mr addr:$dst,
++             (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
++              sub_8bit))>;
++  def : Pat<(store VK2:$src, addr:$dst),
++            (MOV8mr addr:$dst,
++             (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK2:$src, VK16)),
++              sub_8bit))>;
++  def : Pat<(store VK4:$src, addr:$dst),
++            (MOV8mr addr:$dst,
++             (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK4:$src, VK16)),
++              sub_8bit))>;  
++  def : Pat<(store VK8:$src, addr:$dst),
++            (MOV8mr addr:$dst,
++             (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
++              sub_8bit))>;
++  
+   def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
+             (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
+   def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
+@@ -2166,6 +2182,17 @@
+ def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
+           (COPY_TO_REGCLASS VK1:$src, VK64)>;
+ 
++def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
++def : Pat<(store (i1  1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
++def : Pat<(store (i1  0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
++
++def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
++                           (truncstore node:$val, node:$ptr), [{
++  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
++}]>;
++
++def : Pat<(truncstorei1 GR8:$src, addr:$dst),
++          (MOV8mr addr:$dst, GR8:$src)>;
+ 
+ // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
+ let Predicates = [HasAVX512, NoDQI] in {
+@@ -6540,28 +6567,6 @@
+ def v16i1sextv16i32  : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
+ def v8i1sextv8i64  : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
+ 
+-def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
+-def : Pat<(store (i1  1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
+-def : Pat<(store (i1  0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
+-
+-def : Pat<(store VK1:$src, addr:$dst),
+-          (MOV8mr addr:$dst,
+-           (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
+-            sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
+-
+-def : Pat<(store VK8:$src, addr:$dst),
+-          (MOV8mr addr:$dst,
+-           (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
+-            sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
+-
+-def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
+-                           (truncstore node:$val, node:$ptr), [{
+-  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+-}]>;
+-
+-def : Pat<(truncstorei1 GR8:$src, addr:$dst),
+-          (MOV8mr addr:$dst, GR8:$src)>;
+-
+ multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
+ def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
+                   !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
+--- lib/Target/X86/X86InstrInfo.cpp	2016-04-07 01:11:55.016960678 +0300
++++ lib/Target/X86/X86InstrInfo.cpp	2016-04-07 01:13:00.255963353 +0300
+@@ -4286,12 +4286,14 @@
+   return 0;
+ }
+ 
++static bool isMaskRegClass(const TargetRegisterClass *RC) {
++  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
++  return X86::VK16RegClass.hasSubClassEq(RC);
++}
++
+ static bool MaskRegClassContains(unsigned Reg) {
+-  return X86::VK8RegClass.contains(Reg) ||
+-         X86::VK16RegClass.contains(Reg) ||
+-         X86::VK32RegClass.contains(Reg) ||
+-         X86::VK64RegClass.contains(Reg) ||
+-         X86::VK1RegClass.contains(Reg);
++  // All KMASK RegClasses hold the same k registers, can be tested against anyone.
++  return X86::VK16RegClass.contains(Reg);
+ }
+ 
+ static bool GRRegClassContains(unsigned Reg) {
+@@ -4493,15 +4495,28 @@
+   llvm_unreachable("Cannot emit physreg copy instruction");
+ }
+ 
++static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
++                                          bool load) {
++  switch (RC->getSize()) {
++  default:
++    llvm_unreachable("Unknown spill size");
++  case 2:
++    return load ? X86::KMOVWkm : X86::KMOVWmk;
++  case 4:
++    return load ? X86::KMOVDkm : X86::KMOVDmk;
++  case 8:
++    return load ? X86::KMOVQkm : X86::KMOVQmk;
++  }
++}
++
+ static unsigned getLoadStoreRegOpcode(unsigned Reg,
+                                       const TargetRegisterClass *RC,
+                                       bool isStackAligned,
+                                       const X86Subtarget &STI,
+                                       bool load) {
+   if (STI.hasAVX512()) {
+-    if (X86::VK8RegClass.hasSubClassEq(RC)  ||
+-      X86::VK16RegClass.hasSubClassEq(RC))
+-      return load ? X86::KMOVWkm : X86::KMOVWmk;
++    if (isMaskRegClass(RC))
++      return getLoadStoreMaskRegOpcode(RC, load);
+     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
+       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
+     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
+--- lib/Target/X86/X86InstrInfo.td	2016-04-07 01:11:55.018960678 +0300
++++ lib/Target/X86/X86InstrInfo.td	2016-04-07 01:14:17.400966516 +0300
+@@ -728,6 +728,8 @@
+ 
+ //===----------------------------------------------------------------------===//
+ // X86 Instruction Predicate Definitions.
++def TruePredicate : Predicate<"true">;
++
+ def HasCMov      : Predicate<"Subtarget->hasCMov()">;
+ def NoCMov       : Predicate<"!Subtarget->hasCMov()">;
+ 
+--- lib/Target/X86/X86InstrSSE.td	2016-04-07 01:11:55.014960678 +0300
++++ lib/Target/X86/X86InstrSSE.td	2016-04-07 01:14:18.172966548 +0300
+@@ -4273,17 +4273,17 @@
+ //===---------------------------------------------------------------------===//
+ 
+ defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
+-                             SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
++                             SSE_INTALU_ITINS_P, 1, TruePredicate>;
+ defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
+-                             SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
++                             SSE_INTALU_ITINS_P, 1, TruePredicate>;
+ defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
+-                             SSE_INTALU_ITINS_P, 1, NoVLX>;
++                             SSE_INTALU_ITINS_P, 1, TruePredicate>;
+ defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
+-                             SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
++                             SSE_INTALU_ITINS_P, 0, TruePredicate>;
+ defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
+-                             SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
++                             SSE_INTALU_ITINS_P, 0, TruePredicate>;
+ defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
+-                             SSE_INTALU_ITINS_P, 0, NoVLX>;
++                             SSE_INTALU_ITINS_P, 0, TruePredicate>;
+ 
+ //===---------------------------------------------------------------------===//
+ // SSE2 - Packed Integer Shuffle Instructions
+--- lib/Target/X86/X86RegisterInfo.td	2016-04-07 01:11:55.018960678 +0300
++++ lib/Target/X86/X86RegisterInfo.td	2016-04-07 01:13:01.037963385 +0300
+@@ -477,18 +477,18 @@
+                            256, (sequence "YMM%u", 0, 31)>;
+ 
+ // Mask registers
+-def VK1     : RegisterClass<"X86", [i1],    8,  (sequence "K%u", 0, 7)> {let Size = 8;}
+-def VK2     : RegisterClass<"X86", [v2i1],  8,  (add VK1)> {let Size = 8;}
+-def VK4     : RegisterClass<"X86", [v4i1],  8,  (add VK2)> {let Size = 8;}
+-def VK8     : RegisterClass<"X86", [v8i1],  8,  (add VK4)> {let Size = 8;}
++def VK1     : RegisterClass<"X86", [i1],    16,  (sequence "K%u", 0, 7)> {let Size = 16;}
++def VK2     : RegisterClass<"X86", [v2i1],  16,  (add VK1)> {let Size = 16;}
++def VK4     : RegisterClass<"X86", [v4i1],  16,  (add VK2)> {let Size = 16;}
++def VK8     : RegisterClass<"X86", [v8i1],  16,  (add VK4)> {let Size = 16;}
+ def VK16    : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
+ def VK32    : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
+ def VK64    : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
+ 
+-def VK1WM   : RegisterClass<"X86", [i1],    8,  (sub VK1, K0)> {let Size = 8;}
+-def VK2WM   : RegisterClass<"X86", [v2i1],  8,  (sub VK2, K0)> {let Size = 8;}
+-def VK4WM   : RegisterClass<"X86", [v4i1],  8,  (sub VK4, K0)> {let Size = 8;}
+-def VK8WM   : RegisterClass<"X86", [v8i1],  8,  (sub VK8, K0)> {let Size = 8;}
++def VK1WM   : RegisterClass<"X86", [i1],    16,  (sub VK1, K0)> {let Size = 16;}
++def VK2WM   : RegisterClass<"X86", [v2i1],  16,  (sub VK2, K0)> {let Size = 16;}
++def VK4WM   : RegisterClass<"X86", [v4i1],  16,  (sub VK4, K0)> {let Size = 16;}
++def VK8WM   : RegisterClass<"X86", [v8i1],  16,  (sub VK8, K0)> {let Size = 16;}
+ def VK16WM  : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>   {let Size = 16;}
+ def VK32WM  : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
+ def VK64WM  : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}

module.cpp

@@ -2220,9 +2220,9 @@ Module::writeHeader(const char *fn) {
 
     if (g->emitInstrumentation) {
         fprintf(f, "#define ISPC_INSTRUMENTATION 1\n");
-        fprintf(f, "extern \"C\" {\n");
+        fprintf(f, "#if defined(__cplusplus) && (! defined(__ISPC_NO_EXTERN_C) || !__ISPC_NO_EXTERN_C )\nextern \"C\" {\n#endif // __cplusplus\n");
         fprintf(f, "  void ISPCInstrument(const char *fn, const char *note, int line, uint64_t mask);\n");
-        fprintf(f, "}\n");
+        fprintf(f, "#if defined(__cplusplus) && (! defined(__ISPC_NO_EXTERN_C) || !__ISPC_NO_EXTERN_C )\n} /* end extern C */\n#endif // __cplusplus\n");
     }
 
     // end namespace
@@ -2333,9 +2333,9 @@ Module::writeDispatchHeader(DispatchHeaderInfo *DHI) {
 
       if (g->emitInstrumentation) {
         fprintf(f, "#define ISPC_INSTRUMENTATION 1\n");
-        fprintf(f, "extern \"C\" {\n");
+        fprintf(f, "#if defined(__cplusplus) && (! defined(__ISPC_NO_EXTERN_C) || !__ISPC_NO_EXTERN_C )\nextern \"C\" {\n#endif // __cplusplus\n");
         fprintf(f, "  void ISPCInstrument(const char *fn, const char *note, int line, uint64_t mask);\n");
-        fprintf(f, "}\n");
+        fprintf(f, "#if defined(__cplusplus) && (! defined(__ISPC_NO_EXTERN_C) || !__ISPC_NO_EXTERN_C )\n} /* end extern C */\n#endif // __cplusplus\n");
       }
 
       // end namespace
@@ -2809,10 +2809,8 @@ lCreateDispatchFunction(llvm::Module *module, llvm::Function *setISAFunc,
             !g->target->getTreatGenericAsSmth().empty()) {
             if (g->target->getTreatGenericAsSmth() == "knl_generic")
                 dispatchNum = Target::KNL_AVX512;
-            else if (g->target->getTreatGenericAsSmth() == "skx_generic")
-                dispatchNum = Target::SKX;
             else {
-                Error(SourcePos(), "*-generic target can be called only with knl or skx");
+                Error(SourcePos(), "*-generic target can be called only with knl");
                 exit(1);
             }
         }

opt.cpp

@@ -112,6 +112,10 @@
   #include <llvm/Analysis/BasicAliasAnalysis.h>
   #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
 #endif
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_9 // LLVM 3.9+
+  #include "llvm/Transforms/IPO/FunctionAttrs.h"
+  #include "llvm/Transforms/Scalar/GVN.h"
+#endif
 #include <llvm/Analysis/Passes.h>
 #include <llvm/Support/raw_ostream.h>
 #include <llvm/Support/Dwarf.h>
@@ -672,7 +676,10 @@ Optimize(llvm::Module *module, int optLevel) {
         optPM.add(llvm::createInstructionCombiningPass());
         optPM.add(llvm::createCFGSimplificationPass());
         optPM.add(llvm::createPruneEHPass());
-#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_8 // 3.8+
+#if ISPC_LLVM_VERSION >= ISPC_LLVM_3_9 // 3.9+
+        optPM.add(llvm::createPostOrderFunctionAttrsLegacyPass());
+        optPM.add(llvm::createReversePostOrderFunctionAttrsPass());
+#elif ISPC_LLVM_VERSION == ISPC_LLVM_3_8 // 3.8
         optPM.add(llvm::createPostOrderFunctionAttrsPass());
         optPM.add(llvm::createReversePostOrderFunctionAttrsPass());
 #else // 3.7 and earlier

perf.py

@@ -339,7 +339,8 @@ def perf(options1, args):
     if options.perf_target != "":
         test_only_r = " sse2-i32x4 sse2-i32x8 sse4-i32x4 sse4-i32x8 sse4-i16x8 \
                         sse4-i8x16 avx1-i32x4 avx1-i32x8 avx1-i32x16 avx1-i64x4 avx1.1-i32x8 \
-                        avx1.1-i32x16 avx1.1-i64x4 avx2-i32x8 avx2-i32x16 avx2-i64x4 "
+                        avx1.1-i32x16 avx1.1-i64x4 avx2-i32x8 avx2-i32x16 avx2-i64x4 \
+                        avx512knl-i32x16 avx512skx-i32x16 "
         test_only = options.perf_target.split(",")
         for iterator in test_only:
             if not (" " + iterator + " " in test_only_r):

run_tests.py

@@ -270,9 +270,6 @@ def run_test(testname):
                 elif (options.target == "knl-generic"):
                     cc_cmd = "%s -O2 -I. %s %s test_static.cpp -DTEST_SIG=%d %s -o %s" % \
                          (options.compiler_exe, gcc_arch, "-xMIC-AVX512", match, obj_name, exe_name)
-                elif (options.target == "avx512knl-i32x16"):
-                    cc_cmd = "%s -O2 -I. %s %s test_static.cpp -DTEST_SIG=%d %s -o %s" % \
-                         (options.compiler_exe, gcc_arch, "-march=knl", match, obj_name, exe_name)
                 else:
                     cc_cmd = "%s -O2 -I. %s %s test_static.cpp -DTEST_SIG=%d %s -o %s" % \
                          (options.compiler_exe, gcc_arch, gcc_isa, match, obj_name, exe_name)                    

stmt.cpp

@@ -1988,7 +1988,13 @@ ForeachStmt::EmitCode(FunctionEmitContext *ctx) const {
         }
 
         ctx->StoreInst(LLVMFalse, stepIndexAfterMaskedBodyPtr);
-        ctx->BranchInst(bbMaskedBody);
+
+        // check to see if counter != end, otherwise, the next step is not necessary
+        llvm::Value *counter = ctx->LoadInst(uniformCounterPtrs[nDims-1], "counter");
+        llvm::Value *atEnd =
+            ctx->CmpInst(llvm::Instruction::ICmp, llvm::CmpInst::ICMP_NE,
+                         counter, endVals[nDims-1], "at_end");
+        ctx->BranchInst(bbMaskedBody, bbReset[nDims-1], atEnd);
     }
 
     ///////////////////////////////////////////////////////////////////////////

tests/foreach-32.ispc

@@ -0,0 +1,29 @@
+export uniform int width() { return programCount; }
+
+export void f_f(uniform float RET[], uniform float aFOO[]) {
+#define A_BEGIN 11
+#define A_END   14
+#define B_BEGIN 28
+#define B_END   31
+#define C_BEGIN 0
+#define C_END   8
+    uniform int t = 0;
+
+    foreach_tiled (i = A_BEGIN ... A_END, j = B_BEGIN ... B_END, k = C_BEGIN ... C_END) {
+        t++;
+    }
+
+    //the comparison with the expected number of iterations
+    if (programCount == 4)
+        RET[programIndex] = t - 24;
+    else if (programCount == 8)
+        RET[programIndex] = t - 16;
+    else if (programCount == 16)
+        RET[programIndex] = t - 8;
+    else
+        RET[programIndex] = t; //this case is still unknown, error in general
+}
+
+export void result(uniform float RET[]) {
+    RET[programIndex] = 0;
+}