Update build to handle existence of LLVM 3.2 dev branch.
We now compile with LLVM 3.0, 3.1, and 3.2svn.
This commit is contained in:
91
ispc.cpp
91
ispc.cpp
@@ -54,14 +54,8 @@
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#include <llvm/Target/TargetMachine.h>
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#include <llvm/Target/TargetOptions.h>
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#include <llvm/Target/TargetData.h>
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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#include <llvm/Support/TargetRegistry.h>
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#include <llvm/Support/TargetSelect.h>
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#else
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#include <llvm/Target/TargetRegistry.h>
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#include <llvm/Target/TargetSelect.h>
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#include <llvm/Target/SubtargetFeature.h>
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#endif
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#include <llvm/Support/TargetRegistry.h>
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#include <llvm/Support/TargetSelect.h>
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#include <llvm/Support/Host.h>
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Globals *g;
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@@ -114,10 +108,7 @@ lGetSystemISA() {
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static const char *supportedCPUs[] = {
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"atom", "penryn", "core2", "corei7",
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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"corei7-avx"
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#endif
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"atom", "penryn", "core2", "corei7", "corei7-avx"
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};
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@@ -128,14 +119,11 @@ Target::GetTarget(const char *arch, const char *cpu, const char *isa,
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if (cpu != NULL) {
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// If a CPU was specified explicitly, try to pick the best
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// possible ISA based on that.
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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if (!strcmp(cpu, "sandybridge") ||
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!strcmp(cpu, "corei7-avx"))
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isa = "avx";
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else
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#endif
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if (!strcmp(cpu, "corei7") ||
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!strcmp(cpu, "penryn"))
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else if (!strcmp(cpu, "corei7") ||
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!strcmp(cpu, "penryn"))
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isa = "sse4";
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else
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isa = "sse2";
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@@ -277,7 +265,6 @@ Target::GetTarget(const char *arch, const char *cpu, const char *isa,
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t->allOffMaskIsSafe = false;
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t->maskBitCount = 32;
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}
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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else if (!strcasecmp(isa, "avx")) {
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t->isa = Target::AVX;
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t->nativeVectorWidth = 8;
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@@ -296,8 +283,7 @@ Target::GetTarget(const char *arch, const char *cpu, const char *isa,
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t->allOffMaskIsSafe = false;
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t->maskBitCount = 32;
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}
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#endif // LLVM 3.0+
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#if defined(LLVM_3_1svn)
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#ifndef LLVM_3_0
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else if (!strcasecmp(isa, "avx2")) {
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t->isa = Target::AVX2;
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t->nativeVectorWidth = 8;
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@@ -316,7 +302,7 @@ Target::GetTarget(const char *arch, const char *cpu, const char *isa,
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t->allOffMaskIsSafe = false;
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t->maskBitCount = 32;
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}
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#endif // LLVM 3.1
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#endif // !LLVM_3_0
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else {
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fprintf(stderr, "Target ISA \"%s\" is unknown. Choices are: %s\n",
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isa, SupportedTargetISAs());
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@@ -354,13 +340,10 @@ Target::SupportedTargetArchs() {
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const char *
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Target::SupportedTargetISAs() {
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return "sse2, sse2-x2, sse4, sse4-x2"
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#ifndef LLVM_2_9
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", avx, avx-x2"
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#endif // !LLVM_2_9
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#ifdef LLVM_3_1svn
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return "sse2, sse2-x2, sse4, sse4-x2, avx, avx-x2"
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#ifndef LLVM_3_0
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", avx2, avx2-x2"
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#endif // LLVM_3_1svn
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#endif // !LLVM_3_0
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", generic-4, generic-8, generic-16, generic-1";
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}
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@@ -369,10 +352,10 @@ std::string
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Target::GetTripleString() const {
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llvm::Triple triple;
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// Start with the host triple as the default
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#if defined(LLVM_3_1) || defined(LLVM_3_1svn)
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triple.setTriple(llvm::sys::getDefaultTargetTriple());
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#else
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#ifdef LLVM_3_0
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triple.setTriple(llvm::sys::getHostTriple());
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#else
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triple.setTriple(llvm::sys::getDefaultTargetTriple());
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#endif
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// And override the arch in the host triple based on what the user
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@@ -398,37 +381,17 @@ Target::GetTargetMachine() const {
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llvm::Reloc::Model relocModel = generatePIC ? llvm::Reloc::PIC_ :
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llvm::Reloc::Default;
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#if defined(LLVM_3_1svn)
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std::string featuresString = attributes;
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llvm::TargetOptions options;
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#if 0
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// This was breaking e.g. round() on SSE2, where the code we want to
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// run wants to do:
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// x += 0x1.0p23f;
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// x -= 0x1.0p23f;
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// But then LLVM was optimizing this away...
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if (g->opt.fastMath == true)
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options.UnsafeFPMath = 1;
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#endif
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llvm::TargetMachine *targetMachine =
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target->createTargetMachine(triple, cpu, featuresString, options,
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relocModel);
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#elif defined(LLVM_3_0)
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#ifdef LLVM_3_0
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std::string featuresString = attributes;
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llvm::TargetMachine *targetMachine =
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target->createTargetMachine(triple, cpu, featuresString, relocModel);
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#else // LLVM 2.9
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#ifdef ISPC_IS_APPLE
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relocModel = llvm::Reloc::PIC_;
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#endif // ISPC_IS_APPLE
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std::string featuresString = cpu + std::string(",") + attributes;
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#else
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std::string featuresString = attributes;
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llvm::TargetOptions options;
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llvm::TargetMachine *targetMachine =
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target->createTargetMachine(triple, featuresString);
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#ifndef ISPC_IS_WINDOWS
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targetMachine->setRelocationModel(relocModel);
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#endif // !ISPC_IS_WINDOWS
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#endif // LLVM_2_9
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target->createTargetMachine(triple, cpu, featuresString, options,
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relocModel);
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#endif // !LLVM_3_0
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Assert(targetMachine != NULL);
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targetMachine->setAsmVerbosityDefault(true);
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@@ -498,16 +461,11 @@ Target::SizeOf(llvm::Type *type,
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llvm::Value *index[1] = { LLVMInt32(1) };
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llvm::PointerType *ptrType = llvm::PointerType::get(type, 0);
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llvm::Value *voidPtr = llvm::ConstantPointerNull::get(ptrType);
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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llvm::ArrayRef<llvm::Value *> arrayRef(&index[0], &index[1]);
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llvm::Instruction *gep =
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llvm::GetElementPtrInst::Create(voidPtr, arrayRef, "sizeof_gep",
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insertAtEnd);
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#else
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llvm::Instruction *gep =
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llvm::GetElementPtrInst::Create(voidPtr, &index[0], &index[1],
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"sizeof_gep", insertAtEnd);
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#endif
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if (is32Bit || g->opt.force32BitAddressing)
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return new llvm::PtrToIntInst(gep, LLVMTypes::Int32Type,
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"sizeof_int", insertAtEnd);
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@@ -536,16 +494,11 @@ Target::StructOffset(llvm::Type *type, int element,
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llvm::Value *indices[2] = { LLVMInt32(0), LLVMInt32(element) };
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llvm::PointerType *ptrType = llvm::PointerType::get(type, 0);
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llvm::Value *voidPtr = llvm::ConstantPointerNull::get(ptrType);
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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llvm::ArrayRef<llvm::Value *> arrayRef(&indices[0], &indices[2]);
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llvm::Instruction *gep =
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llvm::GetElementPtrInst::Create(voidPtr, arrayRef, "offset_gep",
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insertAtEnd);
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#else
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llvm::Instruction *gep =
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llvm::GetElementPtrInst::Create(voidPtr, &indices[0], &indices[2],
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"offset_gep", insertAtEnd);
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#endif
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if (is32Bit || g->opt.force32BitAddressing)
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return new llvm::PtrToIntInst(gep, LLVMTypes::Int32Type,
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"offset_int", insertAtEnd);
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