working on nvptx
This commit is contained in:
Evghenii
120
builtins/target-avx11-i64x4.ll
Normal file
120
builtins/target-avx11-i64x4.ll
Normal file
@@ -0,0 +1,120 @@
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;; Copyright (c) 2013, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
|
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;; modification, are permitted provided that the following conditions are
|
||||
;; met:
|
||||
;;
|
||||
;; * Redistributions of source code must retain the above copyright
|
||||
;; notice, this list of conditions and the following disclaimer.
|
||||
;;
|
||||
;; * Redistributions in binary form must reproduce the above copyright
|
||||
;; notice, this list of conditions and the following disclaimer in the
|
||||
;; documentation and/or other materials provided with the distribution.
|
||||
;;
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||||
;; * Neither the name of Intel Corporation nor the names of its
|
||||
;; contributors may be used to endorse or promote products derived from
|
||||
;; this software without specific prior written permission.
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||||
;;
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||||
;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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include(`target-avx1-i64x4base.ll')
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ifelse(LLVM_VERSION, `LLVM_3_1', `rdrand_decls()',
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`rdrand_definition()')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int min/max
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define <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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define <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unsigned int min/max
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define <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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define <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; gather
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gen_gather(i8)
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gen_gather(i16)
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gen_gather(i32)
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gen_gather(float)
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gen_gather(i64)
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gen_gather(double)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float/half conversions
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define(`expand_4to8', `
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%$3 = shufflevector <4 x $1> %$2, <4 x $1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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')
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define(`extract_4from8', `
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%$3 = shufflevector <8 x $1> %$2, <8 x $1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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')
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readnone
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; 0 is round nearest even
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readnone
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define <4 x float> @__half_to_float_varying(<4 x i16> %v4) nounwind readnone {
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expand_4to8(i16, v4, v)
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%r = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %v)
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extract_4from8(float, r, ret)
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ret <4 x float> %ret
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}
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define <4 x i16> @__float_to_half_varying(<4 x float> %v4) nounwind readnone {
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expand_4to8(float, v4, v)
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%r = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %v, i32 0)
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extract_4from8(i16, r, ret)
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ret <4 x i16> %ret
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}
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define float @__half_to_float_uniform(i16 %v) nounwind readnone {
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%v1 = bitcast i16 %v to <1 x i16>
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%vv = shufflevector <1 x i16> %v1, <1 x i16> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%rv = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %vv)
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%r = extractelement <8 x float> %rv, i32 0
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ret float %r
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}
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define i16 @__float_to_half_uniform(float %v) nounwind readnone {
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%v1 = bitcast float %v to <1 x float>
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%vv = shufflevector <1 x float> %v1, <1 x float> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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; round to nearest even
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%rv = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %vv, i32 0)
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%r = extractelement <8 x i16> %rv, i32 0
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ret i16 %r
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}
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355
builtins/target-avx2-i64x4.ll
Normal file
355
builtins/target-avx2-i64x4.ll
Normal file
@@ -0,0 +1,355 @@
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;; Copyright (c) 2013, Intel Corporation
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;; All rights reserved.
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||||
;;
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;; Redistribution and use in source and binary forms, with or without
|
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;; modification, are permitted provided that the following conditions are
|
||||
;; met:
|
||||
;;
|
||||
;; * Redistributions of source code must retain the above copyright
|
||||
;; notice, this list of conditions and the following disclaimer.
|
||||
;;
|
||||
;; * Redistributions in binary form must reproduce the above copyright
|
||||
;; notice, this list of conditions and the following disclaimer in the
|
||||
;; documentation and/or other materials provided with the distribution.
|
||||
;;
|
||||
;; * Neither the name of Intel Corporation nor the names of its
|
||||
;; contributors may be used to endorse or promote products derived from
|
||||
;; this software without specific prior written permission.
|
||||
;;
|
||||
;;
|
||||
;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
||||
;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
|
||||
;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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ifelse(LLVM_VERSION, `LLVM_3_1', `',
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`define(`HAVE_GATHER', `1')')
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include(`target-avx1-i64x4base.ll')
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ifelse(LLVM_VERSION, `LLVM_3_1', `rdrand_decls()',
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`rdrand_definition()')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int min/max
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;; declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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;; declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readonly
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define <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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define <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unsigned int min/max
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;; declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readonly
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;; declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readonly
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define <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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define <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float/half conversions
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define(`expand_4to8', `
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%$3 = shufflevector <4 x $1> %$2, <4 x $1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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')
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define(`extract_4from8', `
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%$3 = shufflevector <8 x $1> %$2, <8 x $1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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')
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readnone
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; 0 is round nearest even
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readnone
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define <4 x float> @__half_to_float_varying(<4 x i16> %v4) nounwind readnone {
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expand_4to8(i16, v4, v)
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%r = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %v)
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extract_4from8(float, r, ret)
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ret <4 x float> %ret
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}
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define <4 x i16> @__float_to_half_varying(<4 x float> %v4) nounwind readnone {
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expand_4to8(float, v4, v)
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%r = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %v, i32 0)
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extract_4from8(i16, r, ret)
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ret <4 x i16> %ret
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}
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define float @__half_to_float_uniform(i16 %v) nounwind readnone {
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%v1 = bitcast i16 %v to <1 x i16>
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%vv = shufflevector <1 x i16> %v1, <1 x i16> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%rv = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %vv)
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%r = extractelement <8 x float> %rv, i32 0
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ret float %r
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}
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define i16 @__float_to_half_uniform(float %v) nounwind readnone {
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%v1 = bitcast float %v to <1 x float>
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%vv = shufflevector <1 x float> %v1, <1 x float> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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; round to nearest even
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%rv = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %vv, i32 0)
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%r = extractelement <8 x i16> %rv, i32 0
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ret i16 %r
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; gather
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declare void @llvm.trap() noreturn nounwind
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ifelse(LLVM_VERSION, `LLVM_3_1', `
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gen_gather_factored(i8)
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gen_gather_factored(i16)
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gen_gather_factored(i32)
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gen_gather_factored(float)
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gen_gather_factored(i64)
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gen_gather_factored(double)', `
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gen_gather(i8)
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gen_gather(i16)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 gathers
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declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %target, i8 * %ptr,
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<4 x i32> %indices, <4 x i32> %mask, i8 %scale) readonly nounwind
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declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %target, i8 * %ptr,
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<4 x i64> %indices, <4 x i32> %mask, i8 %scale) readonly nounwind
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define <4 x i32> @__gather_base_offsets32_i32(i8 * %ptr,
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i32 %scale, <4 x i32> %offsets,
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<4 x i64> %vecmask64) nounwind readonly alwaysinline {
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%scale8 = trunc i32 %scale to i8
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%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
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%v = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> undef, i8 * %ptr,
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<4 x i32> %offsets, <4 x i32> %vecmask, i8 %scale8)
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ret <4 x i32> %v
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}
|
||||
|
||||
|
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define <4 x i32> @__gather_base_offsets64_i32(i8 * %ptr,
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i32 %scale, <4 x i64> %offsets,
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<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
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||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
||||
|
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%v = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> undef, i8 * %ptr,
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<4 x i64> %offsets, <4 x i32> %vecmask, i8 %scale8)
|
||||
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x i32> @__gather32_i32(<4 x i32> %ptrs,
|
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<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
|
||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
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|
||||
%v = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> undef, i8 * null,
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<4 x i32> %ptrs, <4 x i32> %vecmask, i8 1)
|
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ret <4 x i32> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x i32> @__gather64_i32(<4 x i64> %ptrs,
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<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
||||
|
||||
%v = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> undef, i8 * null,
|
||||
<4 x i64> %ptrs, <4 x i32> %vecmask, i8 1)
|
||||
|
||||
ret <4 x i32> %v
|
||||
}
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; float gathers
|
||||
|
||||
declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %target, i8 * %ptr,
|
||||
<4 x i32> %indices, <4 x float> %mask, i8 %scale8) readonly nounwind
|
||||
declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %target, i8 * %ptr,
|
||||
<4 x i64> %indices, <4 x float> %mask, i8 %scale8) readonly nounwind
|
||||
|
||||
define <4 x float> @__gather_base_offsets32_float(i8 * %ptr,
|
||||
i32 %scale, <4 x i32> %offsets,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
|
||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
||||
%mask = bitcast <4 x i32> %vecmask to <4 x float>
|
||||
|
||||
%v = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> undef, i8 * %ptr,
|
||||
<4 x i32> %offsets, <4 x float> %mask, i8 %scale8)
|
||||
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x float> @__gather_base_offsets64_float(i8 * %ptr,
|
||||
i32 %scale, <4 x i64> %offsets,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
|
||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
||||
%mask = bitcast <4 x i32> %vecmask to <4 x float>
|
||||
|
||||
%v = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> undef, i8 * %ptr,
|
||||
<4 x i64> %offsets, <4 x float> %mask, i8 %scale8)
|
||||
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x float> @__gather32_float(<4 x i32> %ptrs,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
||||
%mask = bitcast <4 x i32> %vecmask to <4 x float>
|
||||
|
||||
%v = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> undef, i8 * null,
|
||||
<4 x i32> %ptrs, <4 x float> %mask, i8 1)
|
||||
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x float> @__gather64_float(<4 x i64> %ptrs,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%vecmask = trunc <4 x i64> %vecmask64 to <4 x i32>
|
||||
%mask = bitcast <4 x i32> %vecmask to <4 x float>
|
||||
|
||||
%v = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> undef, i8 * null,
|
||||
<4 x i64> %ptrs, <4 x float> %mask, i8 1)
|
||||
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; int64 gathers
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %target, i8 * %ptr,
|
||||
<4 x i32> %indices, <4 x i64> %mask, i8 %scale) readonly nounwind
|
||||
declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %target, i8 * %ptr,
|
||||
<4 x i64> %indices, <4 x i64> %mask, i8 %scale) readonly nounwind
|
||||
|
||||
define <4 x i64> @__gather_base_offsets32_i64(i8 * %ptr,
|
||||
i32 %scale, <4 x i32> %offsets,
|
||||
<4 x i64> %vecmask) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
|
||||
|
||||
%v = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> undef, i8 * %ptr,
|
||||
<4 x i32> %offsets, <4 x i64> %vecmask, i8 %scale8)
|
||||
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x i64> @__gather_base_offsets64_i64(i8 * %ptr,
|
||||
i32 %scale, <4 x i64> %offsets,
|
||||
<4 x i64> %vecmask) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
|
||||
|
||||
%v = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> undef, i8 * %ptr,
|
||||
<4 x i64> %offsets, <4 x i64> %vecmask, i8 %scale8)
|
||||
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x i64> @__gather32_i64(<4 x i32> %ptrs,
|
||||
<4 x i64> %vecmask) nounwind readonly alwaysinline {
|
||||
|
||||
%v = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> undef, i8 * null,
|
||||
<4 x i32> %ptrs, <4 x i64> %vecmask, i8 1)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
|
||||
define <4 x i64> @__gather64_i64(<4 x i64> %ptrs,
|
||||
<4 x i64> %vecmask) nounwind readonly alwaysinline {
|
||||
%v = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> undef, i8 * null,
|
||||
<4 x i64> %ptrs, <4 x i64> %vecmask, i8 1)
|
||||
ret <4 x i64> %v
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; double gathers
|
||||
|
||||
declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %target, i8 * %ptr,
|
||||
<4 x i64> %indices, <4 x double> %mask, i8 %scale) readonly nounwind
|
||||
declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %target, i8 * %ptr,
|
||||
<4 x i32> %indices, <4 x double> %mask, i8 %scale) readonly nounwind
|
||||
|
||||
define <4 x double> @__gather_base_offsets32_double(i8 * %ptr,
|
||||
i32 %scale, <4 x i32> %offsets,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
|
||||
%vecmask = bitcast <4 x i64> %vecmask64 to <4 x double>
|
||||
|
||||
%v = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef, i8 * %ptr,
|
||||
<4 x i32> %offsets, <4 x double> %vecmask, i8 %scale8)
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @__gather_base_offsets64_double(i8 * %ptr,
|
||||
i32 %scale, <4 x i64> %offsets,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%scale8 = trunc i32 %scale to i8
|
||||
%vecmask = bitcast <4 x i64> %vecmask64 to <4 x double>
|
||||
|
||||
%v = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> undef, i8 * %ptr,
|
||||
<4 x i64> %offsets, <4 x double> %vecmask, i8 %scale8)
|
||||
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @__gather32_double(<4 x i32> %ptrs,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%vecmask = bitcast <4 x i64> %vecmask64 to <4 x double>
|
||||
|
||||
%v = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> undef, i8 * null,
|
||||
<4 x i32> %ptrs, <4 x double> %vecmask, i8 1)
|
||||
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
define <4 x double> @__gather64_double(<4 x i64> %ptrs,
|
||||
<4 x i64> %vecmask64) nounwind readonly alwaysinline {
|
||||
%vecmask = bitcast <4 x i64> %vecmask64 to <4 x double>
|
||||
|
||||
%v = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> undef, i8 * null,
|
||||
<4 x i64> %ptrs, <4 x double> %vecmask, i8 1)
|
||||
|
||||
ret <4 x double> %v
|
||||
}
|
||||
|
||||
')
|
||||
@@ -1813,7 +1813,7 @@ define(`stdlib_core', `
|
||||
declare i32 @__fast_masked_vload()
|
||||
|
||||
declare i8* @ISPCAlloc(i8**, i64, i32) nounwind
|
||||
declare void @ISPCLaunch(i8**, i8*, i8*, i32) nounwind
|
||||
declare void @ISPCLaunch(i8**, i8*, i8*, i32,i32,i32) nounwind
|
||||
declare void @ISPCSync(i8*) nounwind
|
||||
declare void @ISPCInstrument(i8*, i8*, i32, i64) nounwind
|
||||
|
||||
|
||||
Reference in New Issue
Block a user