added avx2-i64x4 and avx1.1-i64x4 targets
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egaburov
126
builtins/target-avx11-i64x4.ll
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126
builtins/target-avx11-i64x4.ll
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;; Copyright (c) 2012, Intel Corporation
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;; All rights reserved.
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;;
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;; Redistribution and use in source and binary forms, with or without
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;; modification, are permitted provided that the following conditions are
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;; met:
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;;
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;; * Redistributions of source code must retain the above copyright
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;; notice, this list of conditions and the following disclaimer.
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;;
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;; * Redistributions in binary form must reproduce the above copyright
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;; notice, this list of conditions and the following disclaimer in the
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;; documentation and/or other materials provided with the distribution.
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;;
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;; * Neither the name of Intel Corporation nor the names of its
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;; contributors may be used to endorse or promote products derived from
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;; this software without specific prior written permission.
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;;
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;;
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;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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;; IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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;; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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;; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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;; OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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;; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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;; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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;; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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include(`target-avx1-i64x4base.ll')
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ifelse(LLVM_VERSION, `LLVM_3_0', `rdrand_decls()',
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LLVM_VERSION, `LLVM_3_1', `rdrand_decls()',
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`rdrand_definition()')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int min/max
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define <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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define <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; unsigned int min/max
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define <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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define <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%m = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %m
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; gather
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gen_gather(i8)
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gen_gather(i16)
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gen_gather(i32)
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gen_gather(float)
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gen_gather(i64)
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gen_gather(double)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float/half conversions
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ifelse(LLVM_VERSION, `LLVM_3_0', `
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;; nothing to define...
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', `
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define(`expand_4to8', `
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%$3 = shufflevector <4 x $1> %$2, <4 x $1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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')
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define(`extract_4from8', `
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%$3 = shufflevector <8 x $1> %$2, <8 x $1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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')
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declare <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16>) nounwind readnone
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; 0 is round nearest even
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declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32) nounwind readnone
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define <4 x float> @__half_to_float_varying(<4 x i16> %v4) nounwind readnone {
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expand_4to8(i16, v4, v)
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%r = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %v)
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extract_4from8(float, r, ret)
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ret <4 x float> %ret
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}
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define <4 x i16> @__float_to_half_varying(<4 x float> %v4) nounwind readnone {
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expand_4to8(float, v4, v)
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%r = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %v, i32 0)
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extract_4from8(i16, r, ret)
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ret <4 x i16> %ret
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}
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define float @__half_to_float_uniform(i16 %v) nounwind readnone {
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%v1 = bitcast i16 %v to <1 x i16>
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%vv = shufflevector <1 x i16> %v1, <1 x i16> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%rv = call <8 x float> @llvm.x86.vcvtph2ps.256(<8 x i16> %vv)
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%r = extractelement <8 x float> %rv, i32 0
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ret float %r
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}
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define i16 @__float_to_half_uniform(float %v) nounwind readnone {
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%v1 = bitcast float %v to <1 x float>
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%vv = shufflevector <1 x float> %v1, <1 x float> undef,
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<8 x i32> <i32 0, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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; round to nearest even
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%rv = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %vv, i32 0)
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%r = extractelement <8 x i16> %rv, i32 0
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ret i16 %r
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}
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')
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