Fix ARM NEON output not always being inlined. Also improved scope for ARM NEON optimisation by LLVM, gained about 2% on my code here.
This commit is contained in:
Niall Douglas (s [underscore] sourceforge {at} nedprod [dot] com)
parent
a6952fd651
commit
7af7659ac2
@@ -43,12 +43,12 @@ include(`target-neon-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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define <4 x float> @__half_to_float_varying(<4 x i16> %v) nounwind readnone {
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define <4 x float> @__half_to_float_varying(<4 x i16> %v) nounwind readnone alwaysinline {
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%r = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %v)
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ret <4 x float> %r
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}
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define <4 x i16> @__float_to_half_varying(<4 x float> %v) nounwind readnone {
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define <4 x i16> @__float_to_half_varying(<4 x float> %v) nounwind readnone alwaysinline {
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%r = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %v)
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ret <4 x i16> %r
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}
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@@ -106,13 +106,13 @@ declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwin
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__max_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone {
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<WIDTH x float>) nounwind readnone alwaysinline {
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%r = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %0, <4 x float> %1)
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ret <WIDTH x float> %r
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}
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define <WIDTH x float> @__min_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone {
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<WIDTH x float>) nounwind readnone alwaysinline {
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%r = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %0, <4 x float> %1)
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ret <WIDTH x float> %r
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}
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@@ -122,22 +122,22 @@ declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind read
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declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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define <WIDTH x i32> @__min_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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define <WIDTH x i32> @__min_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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%r = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %r
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}
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define <WIDTH x i32> @__max_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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define <WIDTH x i32> @__max_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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%r = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %r
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}
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define <WIDTH x i32> @__min_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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define <WIDTH x i32> @__min_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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%r = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %r
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}
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define <WIDTH x i32> @__max_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone {
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define <WIDTH x i32> @__max_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone alwaysinline {
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%r = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %r
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}
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@@ -147,7 +147,7 @@ define <WIDTH x i32> @__max_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwin
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__rcp_varying_float(<WIDTH x float> %d) nounwind readnone {
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define <WIDTH x float> @__rcp_varying_float(<WIDTH x float> %d) nounwind readnone alwaysinline {
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%x0 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %d)
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%x0_nr = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %d, <4 x float> %x0)
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%x1 = fmul <4 x float> %x0, %x0_nr
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@@ -159,7 +159,7 @@ define <WIDTH x float> @__rcp_varying_float(<WIDTH x float> %d) nounwind readnon
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declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %d) nounwind readnone {
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define <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %d) nounwind readnone alwaysinline {
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%x0 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %d)
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%x0_2 = fmul <4 x float> %x0, %x0
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%x0_nr = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %d, <4 x float> %x0_2)
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@@ -170,7 +170,7 @@ define <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %d) nounwind readn
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ret <4 x float> %x2
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}
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define float @__rsqrt_uniform_float(float) nounwind readnone {
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define float @__rsqrt_uniform_float(float) nounwind readnone alwaysinline {
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%v1 = bitcast float %0 to <1 x float>
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%vs = shufflevector <1 x float> %v1, <1 x float> undef,
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<4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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@@ -179,7 +179,7 @@ define float @__rsqrt_uniform_float(float) nounwind readnone {
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ret float %r
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}
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define float @__rcp_uniform_float(float) nounwind readnone {
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define float @__rcp_uniform_float(float) nounwind readnone alwaysinline {
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%v1 = bitcast float %0 to <1 x float>
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%vs = shufflevector <1 x float> %v1, <1 x float> undef,
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<4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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@@ -190,7 +190,7 @@ define float @__rcp_uniform_float(float) nounwind readnone {
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
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define <WIDTH x float> @__sqrt_varying_float(<WIDTH x float>) nounwind readnone {
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define <WIDTH x float> @__sqrt_varying_float(<WIDTH x float>) nounwind readnone alwaysinline {
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%result = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
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;; this returns nan for v=0, which is undesirable..
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;; %rsqrt = call <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float> %0)
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@@ -200,7 +200,7 @@ define <WIDTH x float> @__sqrt_varying_float(<WIDTH x float>) nounwind readnone
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declare <4 x double> @llvm.sqrt.v4f64(<4 x double>)
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define <WIDTH x double> @__sqrt_varying_double(<WIDTH x double>) nounwind readnone {
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define <WIDTH x double> @__sqrt_varying_double(<WIDTH x double>) nounwind readnone alwaysinline {
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%r = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %0)
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ret <4 x double> %r
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}
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@@ -208,7 +208,7 @@ define <WIDTH x double> @__sqrt_varying_double(<WIDTH x double>) nounwind readno
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; reductions
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define i64 @__movmsk(<4 x MASK>) nounwind readnone {
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define i64 @__movmsk(<4 x MASK>) nounwind readnone alwaysinline {
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%and_mask = and <4 x MASK> %0, <MASK 1, MASK 2, MASK 4, MASK 8>
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%v01 = shufflevector <4 x i32> %and_mask, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%v23 = shufflevector <4 x i32> %and_mask, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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@@ -264,42 +264,42 @@ define(`neon_reduce', `
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declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define internal float @add_f32(float, float) {
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define internal float @add_f32(float, float) nounwind readnone alwaysinline {
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%r = fadd float %0, %1
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ret float %r
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}
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define float @__reduce_add_float(<4 x float>) nounwind readnone {
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define float @__reduce_add_float(<4 x float>) nounwind readnone alwaysinline {
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neon_reduce(float, @llvm.arm.neon.vpadd.v2f32, @add_f32)
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}
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declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define internal float @min_f32(float, float) {
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define internal float @min_f32(float, float) nounwind readnone alwaysinline {
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%cmp = fcmp olt float %0, %1
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%r = select i1 %cmp, float %0, float %1
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ret float %r
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}
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define float @__reduce_min_float(<4 x float>) nounwind readnone {
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define float @__reduce_min_float(<4 x float>) nounwind readnone alwaysinline {
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neon_reduce(float, @llvm.arm.neon.vpmins.v2f32, @min_f32)
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}
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declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define internal float @max_f32(float, float) {
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define internal float @max_f32(float, float) nounwind readnone alwaysinline {
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%cmp = fcmp ugt float %0, %1
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%r = select i1 %cmp, float %0, float %1
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ret float %r
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}
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define float @__reduce_max_float(<4 x float>) nounwind readnone {
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define float @__reduce_max_float(<4 x float>) nounwind readnone alwaysinline {
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neon_reduce(float, @llvm.arm.neon.vpmaxs.v2f32, @max_f32)
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}
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declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
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define i16 @__reduce_add_int8(<WIDTH x i8>) nounwind readnone {
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define i16 @__reduce_add_int8(<WIDTH x i8>) nounwind readnone alwaysinline {
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%v8 = shufflevector <4 x i8> %0, <4 x i8> zeroinitializer,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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%a16 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %v8)
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@@ -313,7 +313,7 @@ define i16 @__reduce_add_int8(<WIDTH x i8>) nounwind readnone {
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declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
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define i32 @__reduce_add_int16(<WIDTH x i16>) nounwind readnone {
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define i32 @__reduce_add_int16(<WIDTH x i16>) nounwind readnone alwaysinline {
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%a32 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %0)
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%a0 = extractelement <2 x i32> %a32, i32 0
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%a1 = extractelement <2 x i32> %a32, i32 1
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@@ -323,7 +323,7 @@ define i32 @__reduce_add_int16(<WIDTH x i16>) nounwind readnone {
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declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
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define i64 @__reduce_add_int32(<WIDTH x i32>) nounwind readnone {
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define i64 @__reduce_add_int32(<WIDTH x i32>) nounwind readnone alwaysinline {
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%a64 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %0)
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%a0 = extractelement <2 x i64> %a64, i32 0
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%a1 = extractelement <2 x i64> %a64, i32 1
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@@ -333,53 +333,53 @@ define i64 @__reduce_add_int32(<WIDTH x i32>) nounwind readnone {
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declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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define internal i32 @min_si32(i32, i32) {
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define internal i32 @min_si32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp slt i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__reduce_min_int32(<4 x i32>) nounwind readnone {
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define i32 @__reduce_min_int32(<4 x i32>) nounwind readnone alwaysinline {
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neon_reduce(i32, @llvm.arm.neon.vpmins.v2i32, @min_si32)
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}
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declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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define internal i32 @max_si32(i32, i32) {
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define internal i32 @max_si32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp sgt i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__reduce_max_int32(<4 x i32>) nounwind readnone {
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define i32 @__reduce_max_int32(<4 x i32>) nounwind readnone alwaysinline {
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neon_reduce(i32, @llvm.arm.neon.vpmaxs.v2i32, @max_si32)
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}
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declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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define internal i32 @min_ui32(i32, i32) {
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define internal i32 @min_ui32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp ult i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__reduce_min_uint32(<4 x i32>) nounwind readnone {
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define i32 @__reduce_min_uint32(<4 x i32>) nounwind readnone alwaysinline {
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neon_reduce(i32, @llvm.arm.neon.vpmins.v2i32, @min_ui32)
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}
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declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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define internal i32 @max_ui32(i32, i32) {
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define internal i32 @max_ui32(i32, i32) nounwind readnone alwaysinline {
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%cmp = icmp ugt i32 %0, %1
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%r = select i1 %cmp, i32 %0, i32 %1
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ret i32 %r
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}
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define i32 @__reduce_max_uint32(<4 x i32>) nounwind readnone {
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define i32 @__reduce_max_uint32(<4 x i32>) nounwind readnone alwaysinline {
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neon_reduce(i32, @llvm.arm.neon.vpmaxs.v2i32, @max_ui32)
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}
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define double @__reduce_add_double(<4 x double>) nounwind readnone {
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define double @__reduce_add_double(<4 x double>) nounwind readnone alwaysinline {
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%v0 = shufflevector <4 x double> %0, <4 x double> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x double> %0, <4 x double> undef,
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@@ -391,15 +391,15 @@ define double @__reduce_add_double(<4 x double>) nounwind readnone {
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ret double %m
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}
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define double @__reduce_min_double(<4 x double>) nounwind readnone {
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define double @__reduce_min_double(<4 x double>) nounwind readnone alwaysinline {
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reduce4(double, @__min_varying_double, @__min_uniform_double)
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}
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define double @__reduce_max_double(<4 x double>) nounwind readnone {
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define double @__reduce_max_double(<4 x double>) nounwind readnone alwaysinline {
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reduce4(double, @__max_varying_double, @__max_uniform_double)
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}
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define i64 @__reduce_add_int64(<4 x i64>) nounwind readnone {
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define i64 @__reduce_add_int64(<4 x i64>) nounwind readnone alwaysinline {
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%v0 = shufflevector <4 x i64> %0, <4 x i64> undef,
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<2 x i32> <i32 0, i32 1>
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%v1 = shufflevector <4 x i64> %0, <4 x i64> undef,
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@@ -411,19 +411,19 @@ define i64 @__reduce_add_int64(<4 x i64>) nounwind readnone {
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ret i64 %m
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}
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define i64 @__reduce_min_int64(<4 x i64>) nounwind readnone {
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define i64 @__reduce_min_int64(<4 x i64>) nounwind readnone alwaysinline {
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reduce4(i64, @__min_varying_int64, @__min_uniform_int64)
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}
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define i64 @__reduce_max_int64(<4 x i64>) nounwind readnone {
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define i64 @__reduce_max_int64(<4 x i64>) nounwind readnone alwaysinline {
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reduce4(i64, @__max_varying_int64, @__max_uniform_int64)
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}
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define i64 @__reduce_min_uint64(<4 x i64>) nounwind readnone {
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define i64 @__reduce_min_uint64(<4 x i64>) nounwind readnone alwaysinline {
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reduce4(i64, @__min_varying_uint64, @__min_uniform_uint64)
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}
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define i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone {
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define i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone alwaysinline {
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reduce4(i64, @__max_varying_uint64, @__max_uniform_uint64)
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}
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@@ -432,56 +432,56 @@ define i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone {
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declare <4 x i8> @llvm.arm.neon.vrhaddu.v4i8(<4 x i8>, <4 x i8>) nounwind readnone
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define <4 x i8> @__avg_up_uint8(<4 x i8>, <4 x i8>) nounwind readnone {
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define <4 x i8> @__avg_up_uint8(<4 x i8>, <4 x i8>) nounwind readnone alwaysinline {
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%r = call <4 x i8> @llvm.arm.neon.vrhaddu.v4i8(<4 x i8> %0, <4 x i8> %1)
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ret <4 x i8> %r
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}
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declare <4 x i8> @llvm.arm.neon.vrhadds.v4i8(<4 x i8>, <4 x i8>) nounwind readnone
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define <4 x i8> @__avg_up_int8(<4 x i8>, <4 x i8>) nounwind readnone {
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define <4 x i8> @__avg_up_int8(<4 x i8>, <4 x i8>) nounwind readnone alwaysinline {
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%r = call <4 x i8> @llvm.arm.neon.vrhadds.v4i8(<4 x i8> %0, <4 x i8> %1)
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ret <4 x i8> %r
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}
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declare <4 x i8> @llvm.arm.neon.vhaddu.v4i8(<4 x i8>, <4 x i8>) nounwind readnone
|
||||
|
||||
define <4 x i8> @__avg_down_uint8(<4 x i8>, <4 x i8>) nounwind readnone {
|
||||
define <4 x i8> @__avg_down_uint8(<4 x i8>, <4 x i8>) nounwind readnone alwaysinline {
|
||||
%r = call <4 x i8> @llvm.arm.neon.vhaddu.v4i8(<4 x i8> %0, <4 x i8> %1)
|
||||
ret <4 x i8> %r
|
||||
}
|
||||
|
||||
declare <4 x i8> @llvm.arm.neon.vhadds.v4i8(<4 x i8>, <4 x i8>) nounwind readnone
|
||||
|
||||
define <4 x i8> @__avg_down_int8(<4 x i8>, <4 x i8>) nounwind readnone {
|
||||
define <4 x i8> @__avg_down_int8(<4 x i8>, <4 x i8>) nounwind readnone alwaysinline {
|
||||
%r = call <4 x i8> @llvm.arm.neon.vhadds.v4i8(<4 x i8> %0, <4 x i8> %1)
|
||||
ret <4 x i8> %r
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
define <4 x i16> @__avg_up_uint16(<4 x i16>, <4 x i16>) nounwind readnone {
|
||||
define <4 x i16> @__avg_up_uint16(<4 x i16>, <4 x i16>) nounwind readnone alwaysinline {
|
||||
%r = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %0, <4 x i16> %1)
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
define <4 x i16> @__avg_up_int16(<4 x i16>, <4 x i16>) nounwind readnone {
|
||||
define <4 x i16> @__avg_up_int16(<4 x i16>, <4 x i16>) nounwind readnone alwaysinline {
|
||||
%r = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %0, <4 x i16> %1)
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
define <4 x i16> @__avg_down_uint16(<4 x i16>, <4 x i16>) nounwind readnone {
|
||||
define <4 x i16> @__avg_down_uint16(<4 x i16>, <4 x i16>) nounwind readnone alwaysinline {
|
||||
%r = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %0, <4 x i16> %1)
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
declare <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
define <4 x i16> @__avg_down_int16(<4 x i16>, <4 x i16>) nounwind readnone {
|
||||
define <4 x i16> @__avg_down_int16(<4 x i16>, <4 x i16>) nounwind readnone alwaysinline {
|
||||
%r = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %0, <4 x i16> %1)
|
||||
ret <4 x i16> %r
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user