Basic support for AVX2 when building with LLVM3.1svn
For now this target just uses the same builtins-*.ll files as the
regular AVX1 target. Once the gather intrinsic is available from
LLVM, we'll want to have custom target files that call out to that
for gathers. (The integer min/max intrinsics should be wired up to
the __{min,max}_varying_{int,uint}*() builtins at that point as
well.)
This commit is contained in:
@@ -718,6 +718,7 @@ DefineStdlib(SymbolTable *symbolTable, llvm::LLVMContext *ctx, llvm::Module *mod
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}
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}
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break;
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break;
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case Target::AVX:
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case Target::AVX:
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case Target::AVX2:
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switch (g->target.vectorWidth) {
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switch (g->target.vectorWidth) {
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case 8:
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case 8:
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extern unsigned char builtins_bitcode_avx[];
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extern unsigned char builtins_bitcode_avx[];
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26
ispc.cpp
26
ispc.cpp
@@ -161,7 +161,21 @@ Target::GetTarget(const char *arch, const char *cpu, const char *isa,
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t->vectorWidth = 16;
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t->vectorWidth = 16;
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t->attributes = "+avx,+popcnt,+cmov";
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t->attributes = "+avx,+popcnt,+cmov";
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}
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}
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#endif // LLVM 3.0
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#endif // LLVM 3.0+
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#if defined(LLVM_3_1svn)
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else if (!strcasecmp(isa, "avx2")) {
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t->isa = Target::AVX2;
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t->nativeVectorWidth = 8;
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t->vectorWidth = 8;
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t->attributes = "+avx2,+popcnt,+cmov";
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}
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else if (!strcasecmp(isa, "avx2-x2")) {
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t->isa = Target::AVX2;
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t->nativeVectorWidth = 16;
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t->vectorWidth = 16;
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t->attributes = "+avx2,+popcnt,+cmov";
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}
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#endif // LLVM 3.1
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else {
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else {
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fprintf(stderr, "Target ISA \"%s\" is unknown. Choices are: %s\n",
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fprintf(stderr, "Target ISA \"%s\" is unknown. Choices are: %s\n",
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isa, SupportedTargetISAs());
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isa, SupportedTargetISAs());
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@@ -201,9 +215,12 @@ Target::SupportedTargetArchs() {
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const char *
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const char *
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Target::SupportedTargetISAs() {
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Target::SupportedTargetISAs() {
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return "sse2, sse2-x2, sse4, sse4-x2"
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return "sse2, sse2-x2, sse4, sse4-x2"
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#if defined(LLVM_3_0) || defined(LLVM_3_0svn) || defined(LLVM_3_1svn)
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#ifndef LLVM_2.9
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", avx, avx-x2"
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", avx, avx-x2"
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#endif
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#endif !LLVM_2_9
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#ifdef LLVM_3_1svn
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", avx2, avx2-x2"
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#endif // LLVM_3_1svn
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;
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;
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}
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}
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@@ -281,7 +298,8 @@ Target::GetISAString() const {
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return "sse4";
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return "sse4";
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case Target::AVX:
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case Target::AVX:
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return "avx";
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return "avx";
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break;
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case Target::AVX2:
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return "avx2";
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default:
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default:
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FATAL("Unhandled target in GetISAString()");
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FATAL("Unhandled target in GetISAString()");
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}
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}
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2
ispc.h
2
ispc.h
@@ -182,7 +182,7 @@ struct Target {
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flexible/performant of them will apear last in the enumerant. Note
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flexible/performant of them will apear last in the enumerant. Note
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also that __best_available_isa() needs to be updated if ISAs are
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also that __best_available_isa() needs to be updated if ISAs are
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added or the enumerant values are reordered. */
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added or the enumerant values are reordered. */
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enum ISA { SSE2, SSE4, AVX, NUM_ISAS };
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enum ISA { SSE2, SSE4, AVX, AVX2, NUM_ISAS };
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/** Instruction set being compiled to. */
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/** Instruction set being compiled to. */
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ISA isa;
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ISA isa;
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@@ -1169,6 +1169,9 @@ Module::execPreprocessor(const char* infilename, llvm::raw_string_ostream* ostre
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case Target::AVX:
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case Target::AVX:
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opts.addMacroDef("ISPC_TARGET_AVX");
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opts.addMacroDef("ISPC_TARGET_AVX");
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break;
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break;
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case Target::AVX2:
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opts.addMacroDef("ISPC_TARGET_AVX2");
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break;
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default:
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default:
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FATAL("Unhandled target ISA in preprocessor symbol definition");
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FATAL("Unhandled target ISA in preprocessor symbol definition");
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}
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}
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