[AVX512]: try gemeric-16 like builtins
This commit is contained in:
Anton Mitrokhin
@@ -29,265 +29,366 @@
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;; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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;; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; AVX target implementation.
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;;
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;; Please note that this file uses SSE intrinsics, but LLVM generates AVX
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;; instructions, so it doesn't makes sense to change this implemenation.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128-v16:16:16-v32:32:32-v4:128:128";
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define(`MASK',`i1')
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define(`HAVE_GATHER',`1')
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define(`HAVE_SCATTER',`1')
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ctlztz()
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define_prefetches()
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define_shuffles()
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aossoa()
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include(`util.m4')
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stdlib_core()
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scans()
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reduce_equal(WIDTH)
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rdrand_decls()
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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;; broadcast/rotate/shuffle
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declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
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declare <WIDTH x float> @__smear_float(float) nounwind readnone
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declare <WIDTH x double> @__smear_double(double) nounwind readnone
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declare <WIDTH x i8> @__smear_i8(i8) nounwind readnone
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declare <WIDTH x i16> @__smear_i16(i16) nounwind readnone
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declare <WIDTH x i32> @__smear_i32(i32) nounwind readnone
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declare <WIDTH x i64> @__smear_i64(i64) nounwind readnone
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define float @__round_uniform_float(float) nounwind readonly alwaysinline {
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; roundss, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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; the roundss intrinsic is a total mess--docs say:
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;
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; __m128 _mm_round_ss (__m128 a, __m128 b, const int c)
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;
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; b is a 128-bit parameter. The lowest 32 bits are the result of the rounding function
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; on b0. The higher order 96 bits are copied directly from input parameter a. The
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; return value is described by the following equations:
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;
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; r0 = RND(b0)
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; r1 = a1
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; r2 = a2
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; r3 = a3
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;
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; It doesn't matter what we pass as a, since we only need the r0 value
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; here. So we pass the same register for both. Further, only the 0th
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; element of the b parameter matters
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%xi = insertelement <4 x float> undef, float %0, i32 0
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 8)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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declare <WIDTH x float> @__setzero_float() nounwind readnone
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declare <WIDTH x double> @__setzero_double() nounwind readnone
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declare <WIDTH x i8> @__setzero_i8() nounwind readnone
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declare <WIDTH x i16> @__setzero_i16() nounwind readnone
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declare <WIDTH x i32> @__setzero_i32() nounwind readnone
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declare <WIDTH x i64> @__setzero_i64() nounwind readnone
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define float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 9)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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declare <WIDTH x float> @__undef_float() nounwind readnone
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declare <WIDTH x double> @__undef_double() nounwind readnone
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declare <WIDTH x i8> @__undef_i8() nounwind readnone
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declare <WIDTH x i16> @__undef_i16() nounwind readnone
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declare <WIDTH x i32> @__undef_i32() nounwind readnone
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declare <WIDTH x i64> @__undef_i64() nounwind readnone
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define float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 10)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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declare <WIDTH x float> @__broadcast_float(<WIDTH x float>, i32) nounwind readnone
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declare <WIDTH x double> @__broadcast_double(<WIDTH x double>, i32) nounwind readnone
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declare <WIDTH x i8> @__broadcast_i8(<WIDTH x i8>, i32) nounwind readnone
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declare <WIDTH x i16> @__broadcast_i16(<WIDTH x i16>, i32) nounwind readnone
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declare <WIDTH x i32> @__broadcast_i32(<WIDTH x i32>, i32) nounwind readnone
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declare <WIDTH x i64> @__broadcast_i64(<WIDTH x i64>, i32) nounwind readnone
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declare <WIDTH x i8> @__rotate_i8(<WIDTH x i8>, i32) nounwind readnone
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declare <WIDTH x i16> @__rotate_i16(<WIDTH x i16>, i32) nounwind readnone
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declare <WIDTH x float> @__rotate_float(<WIDTH x float>, i32) nounwind readnone
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declare <WIDTH x i32> @__rotate_i32(<WIDTH x i32>, i32) nounwind readnone
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declare <WIDTH x double> @__rotate_double(<WIDTH x double>, i32) nounwind readnone
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declare <WIDTH x i64> @__rotate_i64(<WIDTH x i64>, i32) nounwind readnone
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declare <WIDTH x i8> @__shift_i8(<WIDTH x i8>, i32) nounwind readnone
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declare <WIDTH x i16> @__shift_i16(<WIDTH x i16>, i32) nounwind readnone
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declare <WIDTH x float> @__shift_float(<WIDTH x float>, i32) nounwind readnone
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declare <WIDTH x i32> @__shift_i32(<WIDTH x i32>, i32) nounwind readnone
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declare <WIDTH x double> @__shift_double(<WIDTH x double>, i32) nounwind readnone
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declare <WIDTH x i64> @__shift_i64(<WIDTH x i64>, i32) nounwind readnone
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declare <WIDTH x i8> @__shuffle_i8(<WIDTH x i8>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i8> @__shuffle2_i8(<WIDTH x i8>, <WIDTH x i8>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x i16> @__shuffle_i16(<WIDTH x i16>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i16> @__shuffle2_i16(<WIDTH x i16>, <WIDTH x i16>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x float> @__shuffle_float(<WIDTH x float>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x float> @__shuffle2_float(<WIDTH x float>, <WIDTH x float>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x i32> @__shuffle_i32(<WIDTH x i32>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x i32> @__shuffle2_i32(<WIDTH x i32>, <WIDTH x i32>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x double> @__shuffle_double(<WIDTH x double>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x double> @__shuffle2_double(<WIDTH x double>,
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<WIDTH x double>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i64> @__shuffle_i64(<WIDTH x i64>,
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<WIDTH x i32>) nounwind readnone
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declare <WIDTH x i64> @__shuffle2_i64(<WIDTH x i64>, <WIDTH x i64>,
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<WIDTH x i32>) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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;; aos/soa
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declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
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define double @__round_uniform_double(double) nounwind readonly alwaysinline {
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%xi = insertelement <2 x double> undef, double %0, i32 0
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 8)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundsd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundsd, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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declare void @__soa_to_aos3_float(<WIDTH x float> %v0, <WIDTH x float> %v1,
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<WIDTH x float> %v2, float * noalias %p) nounwind
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declare void @__aos_to_soa3_float(float * noalias %p, <WIDTH x float> * %out0,
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<WIDTH x float> * %out1, <WIDTH x float> * %out2) nounwind
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declare void @__soa_to_aos4_float(<WIDTH x float> %v0, <WIDTH x float> %v1,
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<WIDTH x float> %v2, <WIDTH x float> %v3,
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float * noalias %p) nounwind
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declare void @__aos_to_soa4_float(float * noalias %p, <WIDTH x float> * noalias %out0,
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<WIDTH x float> * noalias %out1,
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<WIDTH x float> * noalias %out2,
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<WIDTH x float> * noalias %out3) nounwind
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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;; half conversion routines
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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define float @__rcp_uniform_float(float) nounwind readonly alwaysinline {
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; do the rcpss call
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; uniform float iv = extract(__rcp_u(v), 0);
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; return iv * (2. - v * iv);
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%vecval = insertelement <4 x float> undef, float %0, i32 0
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%call = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecval)
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%scall = extractelement <4 x float> %call, i32 0
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; do one N-R iteration to improve precision, as above
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%v_iv = fmul float %0, %scall
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%two_minus = fsub float 2., %v_iv
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%iv_mul = fmul float %scall, %two_minus
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ret float %iv_mul
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}
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declare float @__half_to_float_uniform(i16 %v) nounwind readnone
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declare <WIDTH x float> @__half_to_float_varying(<WIDTH x i16> %v) nounwind readnone
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declare i16 @__float_to_half_uniform(float %v) nounwind readnone
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declare <WIDTH x i16> @__float_to_half_varying(<WIDTH x float> %v) nounwind readnone
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rsqrt
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;; math
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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declare void @__fastmath() nounwind
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define float @__rsqrt_uniform_float(float) nounwind readonly alwaysinline {
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; uniform float is = extract(__rsqrt_u(v), 0);
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%v = insertelement <4 x float> undef, float %0, i32 0
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%vis = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %v)
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%is = extractelement <4 x float> %vis, i32 0
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;; round/floor/ceil
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul float %0, %is
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%v_is_is = fmul float %v_is, %is
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%three_sub = fsub float 3., %v_is_is
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%is_mul = fmul float %is, %three_sub
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%half_scale = fmul float 0.5, %is_mul
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ret float %half_scale
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}
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declare float @__round_uniform_float(float) nounwind readnone
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declare float @__floor_uniform_float(float) nounwind readnone
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declare float @__ceil_uniform_float(float) nounwind readnone
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declare double @__round_uniform_double(double) nounwind readnone
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declare double @__floor_uniform_double(double) nounwind readnone
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declare double @__ceil_uniform_double(double) nounwind readnone
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declare <WIDTH x float> @__round_varying_float(<WIDTH x float>) nounwind readnone
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declare <WIDTH x float> @__floor_varying_float(<WIDTH x float>) nounwind readnone
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declare <WIDTH x float> @__ceil_varying_float(<WIDTH x float>) nounwind readnone
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declare <WIDTH x double> @__round_varying_double(<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__floor_varying_double(<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__ceil_varying_double(<WIDTH x double>) nounwind readnone
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;; min/max
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declare float @__max_uniform_float(float, float) nounwind readnone
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declare float @__min_uniform_float(float, float) nounwind readnone
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declare i32 @__min_uniform_int32(i32, i32) nounwind readnone
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declare i32 @__max_uniform_int32(i32, i32) nounwind readnone
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declare i32 @__min_uniform_uint32(i32, i32) nounwind readnone
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declare i32 @__max_uniform_uint32(i32, i32) nounwind readnone
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declare i64 @__min_uniform_int64(i64, i64) nounwind readnone
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declare i64 @__max_uniform_int64(i64, i64) nounwind readnone
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declare i64 @__min_uniform_uint64(i64, i64) nounwind readnone
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declare i64 @__max_uniform_uint64(i64, i64) nounwind readnone
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declare double @__min_uniform_double(double, double) nounwind readnone
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declare double @__max_uniform_double(double, double) nounwind readnone
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declare <WIDTH x float> @__max_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone
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declare <WIDTH x float> @__min_varying_float(<WIDTH x float>,
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<WIDTH x float>) nounwind readnone
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declare <WIDTH x i32> @__min_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i32> @__max_varying_int32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i32> @__min_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i32> @__max_varying_uint32(<WIDTH x i32>, <WIDTH x i32>) nounwind readnone
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declare <WIDTH x i64> @__min_varying_int64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone
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declare <WIDTH x i64> @__max_varying_int64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone
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declare <WIDTH x i64> @__min_varying_uint64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone
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declare <WIDTH x i64> @__max_varying_uint64(<WIDTH x i64>, <WIDTH x i64>) nounwind readnone
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declare <WIDTH x double> @__min_varying_double(<WIDTH x double>,
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<WIDTH x double>) nounwind readnone
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declare <WIDTH x double> @__max_varying_double(<WIDTH x double>,
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<WIDTH x double>) nounwind readnone
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;; sqrt/rsqrt/rcp
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declare float @__rsqrt_uniform_float(float) nounwind readnone
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declare float @__rcp_uniform_float(float) nounwind readnone
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declare float @__sqrt_uniform_float(float) nounwind readnone
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declare <WIDTH x float> @__rcp_varying_float(<WIDTH x float>) nounwind readnone
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declare <WIDTH x float> @__rsqrt_varying_float(<WIDTH x float>) nounwind readnone
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declare <WIDTH x float> @__sqrt_varying_float(<WIDTH x float>) nounwind readnone
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declare double @__sqrt_uniform_double(double) nounwind readnone
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declare <WIDTH x double> @__sqrt_varying_double(<WIDTH x double>) nounwind readnone
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;; bit ops
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declare i32 @__popcnt_int32(i32) nounwind readnone
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declare i64 @__popcnt_int64(i64) nounwind readnone
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declare i32 @__count_trailing_zeros_i32(i32) nounwind readnone
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declare i64 @__count_trailing_zeros_i64(i64) nounwind readnone
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declare i32 @__count_leading_zeros_i32(i32) nounwind readnone
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declare i64 @__count_leading_zeros_i64(i64) nounwind readnone
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; FIXME: need either to wire these up to the 8-wide SVML entrypoints,
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; or, use the macro to call the 4-wide ones twice with our 8-wide
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; vectors...
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;; svml
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include(`svml.m4')
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svml_stubs(float,f,WIDTH)
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svml_stubs(double,d,WIDTH)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; sqrt
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;; reductions
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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declare i64 @__movmsk(<WIDTH x i1>) nounwind readnone
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declare i1 @__any(<WIDTH x i1>) nounwind readnone
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declare i1 @__all(<WIDTH x i1>) nounwind readnone
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declare i1 @__none(<WIDTH x i1>) nounwind readnone
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define float @__sqrt_uniform_float(float) nounwind readonly alwaysinline {
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sse_unary_scalar(ret, 4, float, @llvm.x86.sse.sqrt.ss, %0)
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ret float %ret
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}
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declare i16 @__reduce_add_int8(<WIDTH x i8>) nounwind readnone
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declare i32 @__reduce_add_int16(<WIDTH x i16>) nounwind readnone
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declare float @__reduce_add_float(<WIDTH x float>) nounwind readnone
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declare float @__reduce_min_float(<WIDTH x float>) nounwind readnone
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declare float @__reduce_max_float(<WIDTH x float>) nounwind readnone
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declare i64 @__reduce_add_int32(<WIDTH x i32>) nounwind readnone
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declare i32 @__reduce_min_int32(<WIDTH x i32>) nounwind readnone
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declare i32 @__reduce_max_int32(<WIDTH x i32>) nounwind readnone
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declare i32 @__reduce_min_uint32(<WIDTH x i32>) nounwind readnone
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declare i32 @__reduce_max_uint32(<WIDTH x i32>) nounwind readnone
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declare double @__reduce_add_double(<WIDTH x double>) nounwind readnone
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declare double @__reduce_min_double(<WIDTH x double>) nounwind readnone
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declare double @__reduce_max_double(<WIDTH x double>) nounwind readnone
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declare i64 @__reduce_add_int64(<WIDTH x i64>) nounwind readnone
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declare i64 @__reduce_min_int64(<WIDTH x i64>) nounwind readnone
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declare i64 @__reduce_max_int64(<WIDTH x i64>) nounwind readnone
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declare i64 @__reduce_min_uint64(<WIDTH x i64>) nounwind readnone
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declare i64 @__reduce_max_uint64(<WIDTH x i64>) nounwind readnone
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||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; double precision sqrt
|
||||
;; unaligned loads/loads+broadcasts
|
||||
|
||||
declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
|
||||
|
||||
define double @__sqrt_uniform_double(double) nounwind alwaysinline {
|
||||
sse_unary_scalar(ret, 2, double, @llvm.x86.sse2.sqrt.sd, %0)
|
||||
ret double %ret
|
||||
declare <WIDTH x i8> @__masked_load_i8(i8 * nocapture, <WIDTH x i1> %mask) nounwind readonly
|
||||
declare <WIDTH x i16> @__masked_load_i16(i8 * nocapture, <WIDTH x i1> %mask) nounwind readonly
|
||||
declare <WIDTH x i32> @__masked_load_i32(i8 * nocapture, <WIDTH x i1> %mask) nounwind readonly
|
||||
declare <WIDTH x float> @__masked_load_float(i8 * nocapture, <WIDTH x i1> %mask) nounwind readonly
|
||||
declare <WIDTH x i64> @__masked_load_i64(i8 * nocapture, <WIDTH x i1> %mask) nounwind readonly
|
||||
declare <WIDTH x double> @__masked_load_double(i8 * nocapture, <WIDTH x i1> %mask) nounwind readonly
|
||||
|
||||
declare void @__masked_store_i8(<WIDTH x i8>* nocapture, <WIDTH x i8>,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare void @__masked_store_i16(<WIDTH x i16>* nocapture, <WIDTH x i16>,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare void @__masked_store_i32(<WIDTH x i32>* nocapture, <WIDTH x i32>,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare void @__masked_store_float(<WIDTH x float>* nocapture, <WIDTH x float>,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare void @__masked_store_i64(<WIDTH x i64>* nocapture, <WIDTH x i64>,
|
||||
<WIDTH x i1> %mask) nounwind
|
||||
declare void @__masked_store_double(<WIDTH x double>* nocapture, <WIDTH x double>,
|
||||
<WIDTH x i1> %mask) nounwind
|
||||
|
||||
|
||||
define void @__masked_store_blend_i8(<WIDTH x i8>* nocapture, <WIDTH x i8>,
|
||||
<WIDTH x i1>) nounwind alwaysinline {
|
||||
%v = load PTR_OP_ARGS(`<WIDTH x i8> ') %0
|
||||
%v1 = select <WIDTH x i1> %2, <WIDTH x i8> %1, <WIDTH x i8> %v
|
||||
store <WIDTH x i8> %v1, <WIDTH x i8> * %0
|
||||
ret void
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; fast math mode
|
||||
define void @__masked_store_blend_i16(<WIDTH x i16>* nocapture, <WIDTH x i16>,
|
||||
<WIDTH x i1>) nounwind alwaysinline {
|
||||
%v = load PTR_OP_ARGS(`<WIDTH x i16> ') %0
|
||||
%v1 = select <WIDTH x i1> %2, <WIDTH x i16> %1, <WIDTH x i16> %v
|
||||
store <WIDTH x i16> %v1, <WIDTH x i16> * %0
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.x86.sse.stmxcsr(i8 *) nounwind
|
||||
declare void @llvm.x86.sse.ldmxcsr(i8 *) nounwind
|
||||
define void @__masked_store_blend_i32(<WIDTH x i32>* nocapture, <WIDTH x i32>,
|
||||
<WIDTH x i1>) nounwind alwaysinline {
|
||||
%v = load PTR_OP_ARGS(`<WIDTH x i32> ') %0
|
||||
%v1 = select <WIDTH x i1> %2, <WIDTH x i32> %1, <WIDTH x i32> %v
|
||||
store <WIDTH x i32> %v1, <WIDTH x i32> * %0
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @__fastmath() nounwind alwaysinline {
|
||||
%ptr = alloca i32
|
||||
%ptr8 = bitcast i32 * %ptr to i8 *
|
||||
call void @llvm.x86.sse.stmxcsr(i8 * %ptr8)
|
||||
%oldval = load PTR_OP_ARGS(`i32 ') %ptr
|
||||
define void @__masked_store_blend_float(<WIDTH x float>* nocapture, <WIDTH x float>,
|
||||
<WIDTH x i1>) nounwind alwaysinline {
|
||||
%v = load PTR_OP_ARGS(`<WIDTH x float> ') %0
|
||||
%v1 = select <WIDTH x i1> %2, <WIDTH x float> %1, <WIDTH x float> %v
|
||||
store <WIDTH x float> %v1, <WIDTH x float> * %0
|
||||
ret void
|
||||
}
|
||||
|
||||
; turn on DAZ (64)/FTZ (32768) -> 32832
|
||||
%update = or i32 %oldval, 32832
|
||||
store i32 %update, i32 *%ptr
|
||||
call void @llvm.x86.sse.ldmxcsr(i8 * %ptr8)
|
||||
define void @__masked_store_blend_i64(<WIDTH x i64>* nocapture,
|
||||
<WIDTH x i64>, <WIDTH x i1>) nounwind alwaysinline {
|
||||
%v = load PTR_OP_ARGS(`<WIDTH x i64> ') %0
|
||||
%v1 = select <WIDTH x i1> %2, <WIDTH x i64> %1, <WIDTH x i64> %v
|
||||
store <WIDTH x i64> %v1, <WIDTH x i64> * %0
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @__masked_store_blend_double(<WIDTH x double>* nocapture,
|
||||
<WIDTH x double>, <WIDTH x i1>) nounwind alwaysinline {
|
||||
%v = load PTR_OP_ARGS(`<WIDTH x double> ') %0
|
||||
%v1 = select <WIDTH x i1> %2, <WIDTH x double> %1, <WIDTH x double> %v
|
||||
store <WIDTH x double> %v1, <WIDTH x double> * %0
|
||||
ret void
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; float min/max
|
||||
;; gather/scatter
|
||||
|
||||
define float @__max_uniform_float(float, float) nounwind readonly alwaysinline {
|
||||
%cmp = fcmp ogt float %1, %0
|
||||
%ret = select i1 %cmp, float %1, float %0
|
||||
ret float %ret
|
||||
}
|
||||
define(`gather_scatter', `
|
||||
declare <WIDTH x $1> @__gather_base_offsets32_$1(i8 * nocapture, i32, <WIDTH x i32>,
|
||||
<WIDTH x i1>) nounwind readonly
|
||||
declare <WIDTH x $1> @__gather_base_offsets64_$1(i8 * nocapture, i32, <WIDTH x i64>,
|
||||
<WIDTH x i1>) nounwind readonly
|
||||
declare <WIDTH x $1> @__gather32_$1(<WIDTH x i32>,
|
||||
<WIDTH x i1>) nounwind readonly
|
||||
declare <WIDTH x $1> @__gather64_$1(<WIDTH x i64>,
|
||||
<WIDTH x i1>) nounwind readonly
|
||||
|
||||
define float @__min_uniform_float(float, float) nounwind readonly alwaysinline {
|
||||
%cmp = fcmp ogt float %1, %0
|
||||
%ret = select i1 %cmp, float %0, float %1
|
||||
ret float %ret
|
||||
}
|
||||
declare void @__scatter_base_offsets32_$1(i8* nocapture, i32, <WIDTH x i32>,
|
||||
<WIDTH x $1>, <WIDTH x i1>) nounwind
|
||||
declare void @__scatter_base_offsets64_$1(i8* nocapture, i32, <WIDTH x i64>,
|
||||
<WIDTH x $1>, <WIDTH x i1>) nounwind
|
||||
declare void @__scatter32_$1(<WIDTH x i32>, <WIDTH x $1>,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare void @__scatter64_$1(<WIDTH x i64>, <WIDTH x $1>,
|
||||
<WIDTH x i1>) nounwind
|
||||
')
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; double precision min/max
|
||||
gather_scatter(i8)
|
||||
gather_scatter(i16)
|
||||
gather_scatter(i32)
|
||||
gather_scatter(float)
|
||||
gather_scatter(i64)
|
||||
gather_scatter(double)
|
||||
|
||||
define double @__min_uniform_double(double, double) nounwind readnone alwaysinline {
|
||||
%cmp = fcmp ogt double %1, %0
|
||||
%ret = select i1 %cmp, double %0, double %1
|
||||
ret double %ret
|
||||
}
|
||||
|
||||
define double @__max_uniform_double(double, double) nounwind readnone alwaysinline {
|
||||
%cmp = fcmp ogt double %1, %0
|
||||
%ret = select i1 %cmp, double %1, double %0
|
||||
ret double %ret
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; int min/max
|
||||
|
||||
define i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
|
||||
%cmp = icmp sgt i32 %1, %0
|
||||
%ret = select i1 %cmp, i32 %0, i32 %1
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
|
||||
%cmp = icmp sgt i32 %1, %0
|
||||
%ret = select i1 %cmp, i32 %1, i32 %0
|
||||
ret i32 %ret
|
||||
}
|
||||
declare i32 @__packed_load_active(i32 * nocapture, <WIDTH x i32> * nocapture,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare i32 @__packed_store_active(i32 * nocapture, <WIDTH x i32> %vals,
|
||||
<WIDTH x i1>) nounwind
|
||||
declare i32 @__packed_store_active2(i32 * nocapture, <WIDTH x i32> %vals,
|
||||
<WIDTH x i1>) nounwind
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; unsigned int min/max
|
||||
|
||||
define i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
|
||||
%cmp = icmp ugt i32 %1, %0
|
||||
%ret = select i1 %cmp, i32 %0, i32 %1
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
define i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
|
||||
%cmp = icmp ugt i32 %1, %0
|
||||
%ret = select i1 %cmp, i32 %1, i32 %0
|
||||
ret i32 %ret
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; horizontal ops / reductions
|
||||
|
||||
declare i32 @llvm.ctpop.i32(i32) nounwind readnone
|
||||
|
||||
define i32 @__popcnt_int32(i32) nounwind readonly alwaysinline {
|
||||
%call = call i32 @llvm.ctpop.i32(i32 %0)
|
||||
ret i32 %call
|
||||
}
|
||||
|
||||
declare i64 @llvm.ctpop.i64(i64) nounwind readnone
|
||||
|
||||
define i64 @__popcnt_int64(i64) nounwind readonly alwaysinline {
|
||||
%call = call i64 @llvm.ctpop.i64(i64 %0)
|
||||
ret i64 %call
|
||||
}
|
||||
;; prefetch
|
||||
|
||||
declare void @__prefetch_read_uniform_1(i8 * nocapture) nounwind
|
||||
declare void @__prefetch_read_uniform_2(i8 * nocapture) nounwind
|
||||
declare void @__prefetch_read_uniform_3(i8 * nocapture) nounwind
|
||||
declare void @__prefetch_read_uniform_nt(i8 * nocapture) nounwind
|
||||
|
||||
declare void @__prefetch_read_varying_1(<WIDTH x i64> %addr, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_1_native(i8 * %base, i32 %scale, <WIDTH x i32> %offsets, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_2(<WIDTH x i64> %addr, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_2_native(i8 * %base, i32 %scale, <WIDTH x i32> %offsets, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_3(<WIDTH x i64> %addr, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_3_native(i8 * %base, i32 %scale, <WIDTH x i32> %offsets, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_nt(<WIDTH x i64> %addr, <WIDTH x MASK> %mask) nounwind
|
||||
declare void @__prefetch_read_varying_nt_native(i8 * %base, i32 %scale, <WIDTH x i32> %offsets, <WIDTH x MASK> %mask) nounwind
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; int8/int16 builtins
|
||||
|
||||
define_avgs()
|
||||
declare_nvptx()
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; reciprocals in double precision, if supported
|
||||
|
||||
rsqrtd_decl()
|
||||
rcpd_decl()
|
||||
|
||||
transcendetals_decl()
|
||||
trigonometry_decl()
|
||||
|
||||
Reference in New Issue
Block a user