From 425540922ca24a6d4e44298b6c1e148f1822b151 Mon Sep 17 00:00:00 2001 From: Ilia Filippov Date: Wed, 11 Jun 2014 09:56:36 +0400 Subject: [PATCH] changing +/-feature regulation to CPU regulation --- ispc.cpp | 209 ++++++++++++++++--------------------------------------- 1 file changed, 59 insertions(+), 150 deletions(-) diff --git a/ispc.cpp b/ispc.cpp index 7ea97247..a5834857 100644 --- a/ispc.cpp +++ b/ispc.cpp @@ -241,40 +241,6 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : } } -#if defined(ISPC_ARM_ENABLED) && !defined(__arm__) - if (cpu == NULL && !strncmp(isa, "neon", 4)) - // If we're compiling NEON on an x86 host and the CPU wasn't - // supplied, don't go and set the CPU based on the host... - cpu = "cortex-a9"; -#endif - - if (cpu == NULL) { - std::string hostCPU = llvm::sys::getHostCPUName(); - if (hostCPU.size() > 0) - cpu = strdup(hostCPU.c_str()); - else { - Warning(SourcePos(), "Unable to determine host CPU!\n"); - cpu = "generic"; - } - } - else { - bool foundCPU = false; - for (int i = 0; i < int(sizeof(supportedCPUs) / sizeof(supportedCPUs[0])); - ++i) { - if (!strcmp(cpu, supportedCPUs[i])) { - foundCPU = true; - break; - } - } - if (foundCPU == false) { - Error(SourcePos(), "Error: CPU type \"%s\" unknown. Supported CPUs: " - "%s.", cpu, SupportedCPUs().c_str()); - return; - } - } - - this->m_cpu = cpu; - if (arch == NULL) { #ifdef ISPC_ARM_ENABLED if (!strncmp(isa, "neon", 4)) @@ -308,6 +274,8 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_arch = arch; } + const char * cpuFromIsa; + // Check default LLVM generated targets if (!strcasecmp(isa, "sse2") || !strcasecmp(isa, "sse2-i32x4")) { @@ -316,15 +284,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 16; this->m_dataTypeWidth = 32; this->m_vectorWidth = 4; - this->m_attributes = "+sse,+sse2,-sse3,-sse4a,-ssse3,-popcnt" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",-sse4.1,-sse4.2" -#else - ",-sse41,-sse42" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "core2"; } else if (!strcasecmp(isa, "sse2-x2") || !strcasecmp(isa, "sse2-i32x8")) { @@ -333,15 +295,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 16; this->m_dataTypeWidth = 32; this->m_vectorWidth = 8; - this->m_attributes = "+sse,+sse2,-sse3,-sse4a,-ssse3,-popcnt" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",-sse4.1,-sse4.2" -#else - ",-sse41,-sse42" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "core2"; } else if (!strcasecmp(isa, "sse4") || !strcasecmp(isa, "sse4-i32x4")) { @@ -350,16 +306,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 16; this->m_dataTypeWidth = 32; this->m_vectorWidth = 4; - // TODO: why not sse42 and popcnt? - this->m_attributes = "+sse,+sse2,+sse3,-sse4a,+ssse3,-popcnt,+cmov" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+sse4.1,-sse4.2" -#else - ",+sse41,-sse42" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "corei7"; } else if (!strcasecmp(isa, "sse4x2") || !strcasecmp(isa, "sse4-x2") || @@ -369,15 +318,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 16; this->m_dataTypeWidth = 32; this->m_vectorWidth = 8; - this->m_attributes = "+sse,+sse2,+sse3,-sse4a,+ssse3,-popcnt,+cmov" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+sse4.1,-sse4.2" -#else - ",+sse41,-sse42" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "corei7"; } else if (!strcasecmp(isa, "sse4-i8x16")) { this->m_isa = Target::SSE4; @@ -385,15 +328,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 16; this->m_dataTypeWidth = 8; this->m_vectorWidth = 16; - this->m_attributes = "+sse,+sse2,+sse3,-sse4a,+ssse3,-popcnt,+cmov" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+sse4.1,-sse4.2" -#else - ",+sse41,-sse42" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 8; + cpuFromIsa = "corei7"; } else if (!strcasecmp(isa, "sse4-i16x8")) { this->m_isa = Target::SSE4; @@ -401,15 +338,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 16; this->m_dataTypeWidth = 16; this->m_vectorWidth = 8; - this->m_attributes = "+sse,+sse2,+sse3,-sse4a,+ssse3,-popcnt,+cmov" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+sse4.1,-sse4.2" -#else - ",+sse41,-sse42" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 16; + cpuFromIsa = "corei7"; } else if (!strcasecmp(isa, "generic-4") || !strcasecmp(isa, "generic-x4")) { @@ -499,9 +430,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 4; - this->m_attributes = "+avx,+popcnt,+cmov"; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "corei7-avx"; } else if (!strcasecmp(isa, "avx") || !strcasecmp(isa, "avx1") || @@ -511,9 +442,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 8; - this->m_attributes = "+avx,+popcnt,+cmov"; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "corei7-avx"; } else if (!strcasecmp(isa, "avx-i64x4") || !strcasecmp(isa, "avx1-i64x4")) { @@ -522,9 +453,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 64; this->m_vectorWidth = 4; - this->m_attributes = "+avx,+popcnt,+cmov"; this->m_maskingIsFree = false; this->m_maskBitCount = 64; + cpuFromIsa = "corei7-avx"; } else if (!strcasecmp(isa, "avx-x2") || !strcasecmp(isa, "avx1-x2") || @@ -534,9 +465,9 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 16; - this->m_attributes = "+avx,+popcnt,+cmov"; this->m_maskingIsFree = false; this->m_maskBitCount = 32; + cpuFromIsa = "corei7-avx"; } else if (!strcasecmp(isa, "avx1.1") || !strcasecmp(isa, "avx1.1-i32x8")) { @@ -545,20 +476,11 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 8; - this->m_attributes = "+avx,+popcnt,+cmov,+f16c" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+rdrnd" -#else - ",+rdrand" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; this->m_hasHalf = true; -#if !defined(LLVM_3_1) - // LLVM 3.2+ only this->m_hasRand = true; -#endif + cpuFromIsa = "core-avx-i"; } else if (!strcasecmp(isa, "avx1.1-x2") || !strcasecmp(isa, "avx1.1-i32x16")) { @@ -567,20 +489,11 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 16; - this->m_attributes = "+avx,+popcnt,+cmov,+f16c" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+rdrnd" -#else - ",+rdrand" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; this->m_hasHalf = true; -#if !defined(LLVM_3_1) - // LLVM 3.2+ only this->m_hasRand = true; -#endif + cpuFromIsa = "core-avx-i"; } else if (!strcasecmp(isa, "avx1.1-i64x4")) { this->m_isa = Target::AVX11; @@ -588,20 +501,11 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 64; this->m_vectorWidth = 4; - this->m_attributes = "+avx,+popcnt,+cmov,+f16c" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+rdrnd" -#else - ",+rdrand" -#endif - ; this->m_maskingIsFree = false; this->m_maskBitCount = 64; this->m_hasHalf = true; -#if !defined(LLVM_3_1) - // LLVM 3.2+ only this->m_hasRand = true; -#endif + cpuFromIsa = "core-avx-i"; } else if (!strcasecmp(isa, "avx2") || !strcasecmp(isa, "avx2-i32x8")) { @@ -610,24 +514,12 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 8; - this->m_attributes = "+avx2,+popcnt,+cmov,+f16c" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+rdrnd" -#else - ",+rdrand" -#endif -#ifndef LLVM_3_1 - ",+fma" -#endif // !LLVM_3_1 - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; this->m_hasHalf = true; -#if !defined(LLVM_3_1) - // LLVM 3.2+ only this->m_hasRand = true; this->m_hasGather = true; -#endif + cpuFromIsa = "core-avx2"; } else if (!strcasecmp(isa, "avx2-x2") || !strcasecmp(isa, "avx2-i32x16")) { @@ -636,24 +528,12 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 32; this->m_vectorWidth = 16; - this->m_attributes = "+avx2,+popcnt,+cmov,+f16c" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+rdrnd" -#else - ",+rdrand" -#endif -#ifndef LLVM_3_1 - ",+fma" -#endif // !LLVM_3_1 - ; this->m_maskingIsFree = false; this->m_maskBitCount = 32; this->m_hasHalf = true; -#if !defined(LLVM_3_1) - // LLVM 3.2+ only this->m_hasRand = true; this->m_hasGather = true; -#endif + cpuFromIsa = "core-avx2"; } else if (!strcasecmp(isa, "avx2-i64x4")) { this->m_isa = Target::AVX2; @@ -661,24 +541,12 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : this->m_nativeVectorAlignment = 32; this->m_dataTypeWidth = 64; this->m_vectorWidth = 4; - this->m_attributes = "+avx2,+popcnt,+cmov,+f16c" -#if defined(LLVM_3_4) || defined(LLVM_3_5) - ",+rdrnd" -#else - ",+rdrand" -#endif -#ifndef LLVM_3_1 - ",+fma" -#endif // !LLVM_3_1 - ; this->m_maskingIsFree = false; this->m_maskBitCount = 64; this->m_hasHalf = true; -#if !defined(LLVM_3_1) - // LLVM 3.2+ only this->m_hasRand = true; this->m_hasGather = true; -#endif + cpuFromIsa = "core-avx2"; } #ifdef ISPC_ARM_ENABLED else if (!strcasecmp(isa, "neon-i8x16")) { @@ -722,6 +590,47 @@ Target::Target(const char *arch, const char *cpu, const char *isa, bool pic) : error = true; } +#if defined(ISPC_ARM_ENABLED) && !defined(__arm__) + if (cpu == NULL && !strncmp(isa, "neon", 4)) + + cpu = "cortex-a9"; +#endif + + if (cpu == NULL) { +#ifndef ISPC_ARM_ENABLED + if (isa == NULL) { +#endif + std::string hostCPU = llvm::sys::getHostCPUName(); + if (hostCPU.size() > 0) + cpu = strdup(hostCPU.c_str()); + else { + Warning(SourcePos(), "Unable to determine host CPU!\n"); + cpu = "generic"; + } +#ifndef ISPC_ARM_ENABLED + } + else { + cpu = cpuFromIsa; + } +#endif + } + else { + bool foundCPU = false; + for (int i = 0; i < int(sizeof(supportedCPUs) / sizeof(supportedCPUs[0])); + ++i) { + if (!strcmp(cpu, supportedCPUs[i])) { + foundCPU = true; + break; + } + } + if (foundCPU == false) { + Error(SourcePos(), "Error: CPU type \"%s\" unknown. Supported CPUs: " + "%s.", cpu, SupportedCPUs().c_str()); + return; + } + } + this->m_cpu = cpu; + if (!error) { // Create TargetMachine std::string triple = GetTripleString();