Add avg_{up,down}_int{8,16} routines to stdlib
These compute the average of two given values, rounding up and down, respectively, if the result isn't exact. When possible, these are mapped to target-specific intrinsics (PADD[BW] on IA and VH[R]ADD[US] on NEON.) A subsequent commit will add pattern-matching to generate calls to these intrinsincs when the corresponding patterns are detected in the IR.)
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@@ -506,3 +506,78 @@ define i64 @__reduce_min_uint64(<WIDTH x i64>) nounwind readnone {
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define i64 @__reduce_max_uint64(<WIDTH x i64>) nounwind readnone {
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reduce16(i64, @__max_varying_uint64, @__max_uniform_uint64)
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int8/int16 builtins
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declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @__avg_up_uint8(<16 x i8>, <16 x i8>) nounwind readnone {
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%r = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %r
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}
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declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @__avg_up_int8(<16 x i8>, <16 x i8>) nounwind readnone {
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%r = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %r
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}
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declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @__avg_down_uint8(<16 x i8>, <16 x i8>) nounwind readnone {
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%r = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %r
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}
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declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @__avg_down_int8(<16 x i8>, <16 x i8>) nounwind readnone {
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%r = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %0, <16 x i8> %1)
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ret <16 x i8> %r
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}
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declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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define <16 x i16> @__avg_up_uint16(<16 x i16>, <16 x i16>) nounwind readnone {
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v16tov8(i16, %0, %a0, %b0)
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v16tov8(i16, %1, %a1, %b1)
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%r0 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %a0, <8 x i16> %a1)
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%r1 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %b0, <8 x i16> %b1)
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v8tov16(i16, %r0, %r1, %r)
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ret <16 x i16> %r
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}
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declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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define <16 x i16> @__avg_up_int16(<16 x i16>, <16 x i16>) nounwind readnone {
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v16tov8(i16, %0, %a0, %b0)
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v16tov8(i16, %1, %a1, %b1)
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%r0 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %a0, <8 x i16> %a1)
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%r1 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %b0, <8 x i16> %b1)
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v8tov16(i16, %r0, %r1, %r)
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ret <16 x i16> %r
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}
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declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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define <16 x i16> @__avg_down_uint16(<16 x i16>, <16 x i16>) nounwind readnone {
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v16tov8(i16, %0, %a0, %b0)
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v16tov8(i16, %1, %a1, %b1)
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%r0 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %a0, <8 x i16> %a1)
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%r1 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %b0, <8 x i16> %b1)
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v8tov16(i16, %r0, %r1, %r)
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ret <16 x i16> %r
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}
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declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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define <16 x i16> @__avg_down_int16(<16 x i16>, <16 x i16>) nounwind readnone {
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v16tov8(i16, %0, %a0, %b0)
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v16tov8(i16, %1, %a1, %b1)
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%r0 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %a0, <8 x i16> %a1)
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%r1 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %b0, <8 x i16> %b1)
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v8tov16(i16, %r0, %r1, %r)
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ret <16 x i16> %r
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}
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