IR change for x86 mask load/store instructions in LLVM 3.8 (r250817)
This commit is contained in:
Anton Mitrokhin
@@ -417,18 +417,18 @@ define i64 @__reduce_max_uint64(<16 x i64>) nounwind readnone alwaysinline {
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masked_load(i8, 1)
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masked_load(i16, 2)
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declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8 *, <8 x float> %mask)
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declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8 *, <4 x double> %mask)
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declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8 *, <8 x MfORi32> %mask)
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declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8 *, <4 x MdORi64> %mask)
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define <16 x i32> @__masked_load_i32(i8 *, <16 x i32> %mask) nounwind alwaysinline {
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%floatmask = bitcast <16 x i32> %mask to <16 x float>
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%mask0 = shufflevector <16 x float> %floatmask, <16 x float> undef,
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%floatmask = bitcast <16 x i32> %mask to <16 x MfORi32>
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%mask0 = shufflevector <16 x MfORi32> %floatmask, <16 x MfORi32> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%val0 = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8 * %0, <8 x float> %mask0)
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%mask1 = shufflevector <16 x float> %floatmask, <16 x float> undef,
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%val0 = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8 * %0, <8 x MfORi32> %mask0)
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%mask1 = shufflevector <16 x MfORi32> %floatmask, <16 x MfORi32> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%ptr1 = getelementptr PTR_OP_ARGS(`i8') %0, i32 32 ;; 8x4 bytes = 32
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%val1 = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8 * %ptr1, <8 x float> %mask1)
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%val1 = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8 * %ptr1, <8 x MfORi32> %mask1)
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%retval = shufflevector <8 x float> %val0, <8 x float> %val1,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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@@ -448,18 +448,18 @@ define <16 x i64> @__masked_load_i64(i8 *, <16 x i32> %mask) nounwind alwaysinli
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<8 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11>
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%mask3 = shufflevector <16 x i32> %mask, <16 x i32> undef,
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<8 x i32> <i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
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%mask0d = bitcast <8 x i32> %mask0 to <4 x double>
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%mask1d = bitcast <8 x i32> %mask1 to <4 x double>
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%mask2d = bitcast <8 x i32> %mask2 to <4 x double>
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%mask3d = bitcast <8 x i32> %mask3 to <4 x double>
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%mask0d = bitcast <8 x i32> %mask0 to <4 x MdORi64>
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%mask1d = bitcast <8 x i32> %mask1 to <4 x MdORi64>
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%mask2d = bitcast <8 x i32> %mask2 to <4 x MdORi64>
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%mask3d = bitcast <8 x i32> %mask3 to <4 x MdORi64>
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%val0d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %0, <4 x double> %mask0d)
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%val0d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %0, <4 x MdORi64> %mask0d)
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%ptr1 = getelementptr PTR_OP_ARGS(`i8') %0, i32 32
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%val1d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %ptr1, <4 x double> %mask1d)
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%val1d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %ptr1, <4 x MdORi64> %mask1d)
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%ptr2 = getelementptr PTR_OP_ARGS(`i8') %0, i32 64
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%val2d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %ptr2, <4 x double> %mask2d)
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%val2d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %ptr2, <4 x MdORi64> %mask2d)
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%ptr3 = getelementptr PTR_OP_ARGS(`i8') %0, i32 96
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%val3d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %ptr3, <4 x double> %mask3d)
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%val3d = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8 * %ptr3, <4 x MdORi64> %mask3d)
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%val01 = shufflevector <4 x double> %val0d, <4 x double> %val1d,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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@@ -484,28 +484,28 @@ gen_masked_store(i8)
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gen_masked_store(i16)
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; note that mask is the 2nd parameter, not the 3rd one!!
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declare void @llvm.x86.avx.maskstore.ps.256(i8 *, <8 x float>, <8 x float>)
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declare void @llvm.x86.avx.maskstore.pd.256(i8 *, <4 x double>, <4 x double>)
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declare void @llvm.x86.avx.maskstore.ps.256(i8 *, <8 x MfORi32>, <8 x float>)
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declare void @llvm.x86.avx.maskstore.pd.256(i8 *, <4 x MdORi64>, <4 x double>)
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define void @__masked_store_i32(<16 x i32>* nocapture, <16 x i32>,
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<16 x i32>) nounwind alwaysinline {
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%ptr = bitcast <16 x i32> * %0 to i8 *
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%val = bitcast <16 x i32> %1 to <16 x float>
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%mask = bitcast <16 x i32> %2 to <16 x float>
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%mask = bitcast <16 x i32> %2 to <16 x MfORi32>
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%val0 = shufflevector <16 x float> %val, <16 x float> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%val1 = shufflevector <16 x float> %val, <16 x float> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%mask0 = shufflevector <16 x float> %mask, <16 x float> undef,
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%mask0 = shufflevector <16 x MfORi32> %mask, <16 x MfORi32> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%mask1 = shufflevector <16 x float> %mask, <16 x float> undef,
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%mask1 = shufflevector <16 x MfORi32> %mask, <16 x MfORi32> undef,
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<8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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call void @llvm.x86.avx.maskstore.ps.256(i8 * %ptr, <8 x float> %mask0, <8 x float> %val0)
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call void @llvm.x86.avx.maskstore.ps.256(i8 * %ptr, <8 x MfORi32> %mask0, <8 x float> %val0)
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%ptr1 = getelementptr PTR_OP_ARGS(`i8') %ptr, i32 32
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call void @llvm.x86.avx.maskstore.ps.256(i8 * %ptr1, <8 x float> %mask1, <8 x float> %val1)
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call void @llvm.x86.avx.maskstore.ps.256(i8 * %ptr1, <8 x MfORi32> %mask1, <8 x float> %val1)
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ret void
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}
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@@ -524,10 +524,10 @@ define void @__masked_store_i64(<16 x i64>* nocapture, <16 x i64>,
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<8 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11>
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%mask3 = shufflevector <16 x i32> %mask, <16 x i32> undef,
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<8 x i32> <i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
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%mask0d = bitcast <8 x i32> %mask0 to <4 x double>
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%mask1d = bitcast <8 x i32> %mask1 to <4 x double>
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%mask2d = bitcast <8 x i32> %mask2 to <4 x double>
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%mask3d = bitcast <8 x i32> %mask3 to <4 x double>
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%mask0d = bitcast <8 x i32> %mask0 to <4 x MdORi64>
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%mask1d = bitcast <8 x i32> %mask1 to <4 x MdORi64>
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%mask2d = bitcast <8 x i32> %mask2 to <4 x MdORi64>
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%mask3d = bitcast <8 x i32> %mask3 to <4 x MdORi64>
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%val0 = shufflevector <16 x double> %val, <16 x double> undef,
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<4 x i32> <i32 0, i32 1, i32 2, i32 3>
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@@ -538,13 +538,13 @@ define void @__masked_store_i64(<16 x i64>* nocapture, <16 x i64>,
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%val3 = shufflevector <16 x double> %val, <16 x double> undef,
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<4 x i32> <i32 12, i32 13, i32 14, i32 15>
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr, <4 x double> %mask0d, <4 x double> %val0)
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr, <4 x MdORi64> %mask0d, <4 x double> %val0)
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%ptr1 = getelementptr PTR_OP_ARGS(`i8') %ptr, i32 32
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr1, <4 x double> %mask1d, <4 x double> %val1)
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr1, <4 x MdORi64> %mask1d, <4 x double> %val1)
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%ptr2 = getelementptr PTR_OP_ARGS(`i8') %ptr, i32 64
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr2, <4 x double> %mask2d, <4 x double> %val2)
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr2, <4 x MdORi64> %mask2d, <4 x double> %val2)
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%ptr3 = getelementptr PTR_OP_ARGS(`i8') %ptr, i32 96
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr3, <4 x double> %mask3d, <4 x double> %val3)
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call void @llvm.x86.avx.maskstore.pd.256(i8 * %ptr3, <4 x MdORi64> %mask3d, <4 x double> %val3)
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ret void
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}
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