Changes for sse2 and sse4 in saturation
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@@ -47,6 +47,88 @@ int64minmax()
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include(`target-sse4-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;vector saturation arithmetic
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define <WIDTH x i8> @__padds_vi8(<WIDTH x i8>, <WIDTH x i8>) {
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%v0 = shufflevector <8 x i8> %0, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v1 = shufflevector <8 x i8> %1, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%r16 = call <16 x i8> @llvm.x86.sse2.padds.b(<16 x i8> %v0, <16 x i8> %v1)
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%r = shufflevector <16 x i8> %r16, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <WIDTH x i8> %r
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}
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define <WIDTH x i16> @__padds_vi16(<WIDTH x i16> %a0, <WIDTH x i16> %a1) {
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%res = call <WIDTH x i16> @llvm.x86.sse2.padds.w(<WIDTH x i16> %a0, <WIDTH x i16> %a1)
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ret <WIDTH x i16> %res
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}
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define <WIDTH x i8> @__paddus_vi8(<WIDTH x i8>, <WIDTH x i8>) {
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%v0 = shufflevector <8 x i8> %0, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v1 = shufflevector <8 x i8> %1, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%r16 = call <16 x i8> @llvm.x86.sse2.paddus.b(<16 x i8> %v0, <16 x i8> %v1)
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%r = shufflevector <16 x i8> %r16, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <WIDTH x i8> %r
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}
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define <WIDTH x i16> @__paddus_vi16(<WIDTH x i16> %a0, <WIDTH x i16> %a1) {
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%res = call <WIDTH x i16> @llvm.x86.sse2.paddus.w(<WIDTH x i16> %a0, <WIDTH x i16> %a1)
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ret <WIDTH x i16> %res
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}
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define <WIDTH x i8> @__psubs_vi8(<WIDTH x i8>, <WIDTH x i8>) {
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%v0 = shufflevector <8 x i8> %0, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v1 = shufflevector <8 x i8> %1, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%r16 = call <16 x i8> @llvm.x86.sse2.psubs.b(<16 x i8> %v0, <16 x i8> %v1)
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%r = shufflevector <16 x i8> %r16, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <WIDTH x i8> %r
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}
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define <WIDTH x i16> @__psubs_vi16(<WIDTH x i16> %a0, <WIDTH x i16> %a1) {
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%res = call <WIDTH x i16> @llvm.x86.sse2.psubs.w(<WIDTH x i16> %a0, <WIDTH x i16> %a1)
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ret <WIDTH x i16> %res
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}
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define <WIDTH x i8> @__psubus_vi8(<WIDTH x i8>, <WIDTH x i8>) {
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%v0 = shufflevector <8 x i8> %0, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%v1 = shufflevector <8 x i8> %1, <8 x i8> undef,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
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i32 undef, i32 undef, i32 undef, i32 undef,
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i32 undef, i32 undef, i32 undef, i32 undef>
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%r16 = call <16 x i8> @llvm.x86.sse2.psubus.b(<16 x i8> %v0, <16 x i8> %v1)
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%r = shufflevector <16 x i8> %r16, <16 x i8> undef,
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<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <WIDTH x i8> %r
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}
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define <WIDTH x i16> @__psubus_vi16(<WIDTH x i16> %a0, <WIDTH x i16> %a1) {
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%res = call <WIDTH x i16> @llvm.x86.sse2.psubus.w(<WIDTH x i16> %a0, <WIDTH x i16> %a1)
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ret <WIDTH x i16> %res
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; half conversion routines
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