Add "double-wide" sse2-x2 target.
i.e. run 8 program instances together, along the lines of the double-pumped sse4-x2 target.
This commit is contained in:
Matt Pharr
380
builtins-sse4.ll
380
builtins-sse4.ll
@@ -36,15 +36,68 @@
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stdlib_core(4)
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packed_load_and_store(4)
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scans(4)
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int64minmax(4)
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; Define the stuff that can be done with base SSE1/SSE2 instructions
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include(`builtins-sse.ll')
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include(`builtins-sse4-common.ll')
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rcp
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declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>) nounwind readnone
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define internal <4 x float> @__rcp_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %0)
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; do one N-R iteration to improve precision
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; float iv = __rcp_v(v);
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; return iv * (2. - v * iv);
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%v_iv = fmul <4 x float> %0, %call
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%two_minus = fsub <4 x float> <float 2., float 2., float 2., float 2.>, %v_iv
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%iv_mul = fmul <4 x float> %call, %two_minus
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ret <4 x float> %iv_mul
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; rsqrt
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declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>) nounwind readnone
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define internal <4 x float> @__rsqrt_varying_float(<4 x float> %v) nounwind readonly alwaysinline {
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; float is = __rsqrt_v(v);
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%is = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %v)
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; Newton-Raphson iteration to improve precision
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; return 0.5 * is * (3. - (v * is) * is);
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%v_is = fmul <4 x float> %v, %is
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%v_is_is = fmul <4 x float> %v_is, %is
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%three_sub = fsub <4 x float> <float 3., float 3., float 3., float 3.>, %v_is_is
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%is_mul = fmul <4 x float> %is, %three_sub
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%half_scale = fmul <4 x float> <float 0.5, float 0.5, float 0.5, float 0.5>, %is_mul
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ret <4 x float> %half_scale
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; sqrt
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declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
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define internal <4 x float> @__sqrt_varying_float(<4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %0)
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ret <4 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision sqrt
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declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>) nounwind readnone
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define internal <4 x double> @__sqrt_varying_double(<4 x double>) nounwind alwaysinline {
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unary2to4(ret, double, @llvm.x86.sse2.sqrt.pd, %0)
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ret <4 x double> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding floats
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declare <4 x float> @llvm.x86.sse41.round.ps(<4 x float>, i32) nounwind readnone
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declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
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define internal <4 x float> @__round_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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@@ -52,173 +105,164 @@ define internal <4 x float> @__round_varying_float(<4 x float>) nounwind readonl
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ret <4 x float> %call
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}
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define internal float @__round_uniform_float(float) nounwind readonly alwaysinline {
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; roundss, round mode nearest 0b00 | don't signal precision exceptions 0b1000 = 8
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; the roundss intrinsic is a total mess--docs say:
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;
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; __m128 _mm_round_ss (__m128 a, __m128 b, const int c)
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;
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; b is a 128-bit parameter. The lowest 32 bits are the result of the rounding function
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; on b0. The higher order 96 bits are copied directly from input parameter a. The
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; return value is described by the following equations:
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;
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; r0 = RND(b0)
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; r1 = a1
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; r2 = a2
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; r3 = a3
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;
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; It doesn't matter what we pass as a, since we only need the r0 value
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; here. So we pass the same register for both. Further, only the 0th
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; element of the b parameter matters
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%xi = insertelement <4 x float> undef, float %0, i32 0
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 8)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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define internal <4 x float> @__floor_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 9)
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ret <4 x float> %call
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}
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define internal float @__floor_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round down 0b01 | don't signal precision exceptions 0b1010 = 9
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 9)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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define internal <4 x float> @__ceil_varying_float(<4 x float>) nounwind readonly alwaysinline {
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%call = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %0, i32 10)
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ret <4 x float> %call
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}
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define internal float @__ceil_uniform_float(float) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <4 x float> undef, float %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %xi, <4 x float> %xi, i32 10)
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%rs = extractelement <4 x float> %xr, i32 0
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ret float %rs
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; rounding doubles
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declare <2 x double> @llvm.x86.sse41.round.pd(<2 x double>, i32) nounwind readnone
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declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
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define internal <4 x double> @__round_varying_double(<4 x double>) nounwind readonly alwaysinline {
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round2to4double(%0, 8)
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}
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define internal double @__round_uniform_double(double) nounwind readonly alwaysinline {
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%xi = insertelement <2 x double> undef, double %0, i32 0
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 8)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define internal <4 x double> @__floor_varying_double(<4 x double>) nounwind readonly alwaysinline {
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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round2to4double(%0, 9)
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}
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define internal double @__floor_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundpd, round down 0b01 | don't signal precision exceptions 0b1001 = 9
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 9)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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}
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define internal <4 x double> @__ceil_varying_double(<4 x double>) nounwind readonly alwaysinline {
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; roundpd, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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round2to4double(%0, 10)
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}
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define internal double @__ceil_uniform_double(double) nounwind readonly alwaysinline {
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; see above for round_ss instrinsic discussion...
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%xi = insertelement <2 x double> undef, double %0, i32 0
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; roundps, round up 0b10 | don't signal precision exceptions 0b1010 = 10
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%xr = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %xi, <2 x double> %xi, i32 10)
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%rs = extractelement <2 x double> %xr, i32 0
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ret double %rs
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; float min/max
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declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
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define internal <4 x float> @__max_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %call
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}
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define internal <4 x float> @__min_varying_float(<4 x float>, <4 x float>) nounwind readonly alwaysinline {
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%call = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %call
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; int32 min/max
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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define internal <4 x i32> @__min_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__min_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pminsd, %0, %1)
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ret i32 %ret
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}
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define internal <4 x i32> @__max_varying_int32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__max_uniform_int32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pmaxsd, %0, %1)
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ret i32 %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; unsigned int min/max
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declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
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define internal <4 x i32> @__min_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__min_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pminud, %0, %1)
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ret i32 %ret
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}
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define internal <4 x i32> @__max_varying_uint32(<4 x i32>, <4 x i32>) nounwind readonly alwaysinline {
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%call = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %call
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}
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define internal i32 @__max_uniform_uint32(i32, i32) nounwind readonly alwaysinline {
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sse_binary_scalar(ret, 4, i32, @llvm.x86.sse41.pmaxud, %0, %1)
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ret i32 %ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; double precision min/max
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declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
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declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
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define internal <4 x double> @__min_varying_double(<4 x double>, <4 x double>) nounwind readnone {
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binary2to4(ret, double, @llvm.x86.sse2.min.pd, %0, %1)
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ret <4 x double> %ret
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}
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define internal <4 x double> @__max_varying_double(<4 x double>, <4 x double>) nounwind readnone {
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binary2to4(ret, double, @llvm.x86.sse2.max.pd, %0, %1)
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ret <4 x double> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; svml stuff
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declare <4 x float> @__svml_sinf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_cosf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_sincosf4(<4 x float> *, <4 x float>) nounwind readnone
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declare <4 x float> @__svml_tanf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_atanf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_atan2f4(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @__svml_expf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_logf4(<4 x float>) nounwind readnone
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declare <4 x float> @__svml_powf4(<4 x float>, <4 x float>) nounwind readnone
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define internal <4 x float> @__svml_sin(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_sinf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_cos(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_cosf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal void @__svml_sincos(<4 x float>, <4 x float> *, <4 x float> *) nounwind readnone alwaysinline {
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%s = call <4 x float> @__svml_sincosf4(<4 x float> * %2, <4 x float> %0)
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store <4 x float> %s, <4 x float> * %1
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ret void
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}
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define internal <4 x float> @__svml_tan(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_tanf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_atan(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_atanf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_atan2(<4 x float>, <4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_atan2f4(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_exp(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_expf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_log(<4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_logf4(<4 x float> %0)
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ret <4 x float> %ret
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}
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define internal <4 x float> @__svml_pow(<4 x float>, <4 x float>) nounwind readnone alwaysinline {
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%ret = call <4 x float> @__svml_powf4(<4 x float> %0, <4 x float> %1)
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ret <4 x float> %ret
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; horizontal ops / reductions
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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define internal i32 @__popcnt_int32(i32) nounwind readonly alwaysinline {
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%call = call i32 @llvm.ctpop.i32(i32 %0)
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ret i32 %call
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}
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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define internal i64 @__popcnt_int64(i64) nounwind readonly alwaysinline {
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%call = call i64 @llvm.ctpop.i64(i64 %0)
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ret i64 %call
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define internal i32 @__movmsk(<4 x i32>) nounwind readnone alwaysinline {
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%floatmask = bitcast <4 x i32> %0 to <4 x float>
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%v = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %floatmask) nounwind readnone
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ret i32 %v
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}
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declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
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@@ -230,6 +274,96 @@ define internal float @__reduce_add_float(<4 x float>) nounwind readonly alwaysi
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ret float %scalar
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}
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define internal float @__reduce_min_float(<4 x float>) nounwind readnone {
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reduce4(float, @__min_varying_float, @__min_uniform_float)
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}
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define internal float @__reduce_max_float(<4 x float>) nounwind readnone {
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reduce4(float, @__max_varying_float, @__max_uniform_float)
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}
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define internal i32 @__reduce_add_int32(<4 x i32> %v) nounwind readnone {
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%v1 = shufflevector <4 x i32> %v, <4 x i32> undef,
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<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%m1 = add <4 x i32> %v1, %v
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%m1a = extractelement <4 x i32> %m1, i32 0
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%m1b = extractelement <4 x i32> %m1, i32 1
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%sum = add i32 %m1a, %m1b
|
||||
ret i32 %sum
|
||||
}
|
||||
|
||||
define internal i32 @__reduce_min_int32(<4 x i32>) nounwind readnone {
|
||||
reduce4(i32, @__min_varying_int32, @__min_uniform_int32)
|
||||
}
|
||||
|
||||
define internal i32 @__reduce_max_int32(<4 x i32>) nounwind readnone {
|
||||
reduce4(i32, @__max_varying_int32, @__max_uniform_int32)
|
||||
}
|
||||
|
||||
define internal i32 @__reduce_add_uint32(<4 x i32> %v) nounwind readnone {
|
||||
%r = call i32 @__reduce_add_int32(<4 x i32> %v)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define internal i32 @__reduce_min_uint32(<4 x i32>) nounwind readnone {
|
||||
reduce4(i32, @__min_varying_uint32, @__min_uniform_uint32)
|
||||
}
|
||||
|
||||
define internal i32 @__reduce_max_uint32(<4 x i32>) nounwind readnone {
|
||||
reduce4(i32, @__max_varying_uint32, @__max_uniform_uint32)
|
||||
}
|
||||
|
||||
|
||||
define internal double @__reduce_add_double(<4 x double>) nounwind readnone {
|
||||
%v0 = shufflevector <4 x double> %0, <4 x double> undef,
|
||||
<2 x i32> <i32 0, i32 1>
|
||||
%v1 = shufflevector <4 x double> %0, <4 x double> undef,
|
||||
<2 x i32> <i32 2, i32 3>
|
||||
%sum = fadd <2 x double> %v0, %v1
|
||||
%e0 = extractelement <2 x double> %sum, i32 0
|
||||
%e1 = extractelement <2 x double> %sum, i32 1
|
||||
%m = fadd double %e0, %e1
|
||||
ret double %m
|
||||
}
|
||||
|
||||
define internal double @__reduce_min_double(<4 x double>) nounwind readnone {
|
||||
reduce4(double, @__min_varying_double, @__min_uniform_double)
|
||||
}
|
||||
|
||||
define internal double @__reduce_max_double(<4 x double>) nounwind readnone {
|
||||
reduce4(double, @__max_varying_double, @__max_uniform_double)
|
||||
}
|
||||
|
||||
define internal i64 @__reduce_add_int64(<4 x i64>) nounwind readnone {
|
||||
%v0 = shufflevector <4 x i64> %0, <4 x i64> undef,
|
||||
<2 x i32> <i32 0, i32 1>
|
||||
%v1 = shufflevector <4 x i64> %0, <4 x i64> undef,
|
||||
<2 x i32> <i32 2, i32 3>
|
||||
%sum = add <2 x i64> %v0, %v1
|
||||
%e0 = extractelement <2 x i64> %sum, i32 0
|
||||
%e1 = extractelement <2 x i64> %sum, i32 1
|
||||
%m = add i64 %e0, %e1
|
||||
ret i64 %m
|
||||
}
|
||||
|
||||
define internal i64 @__reduce_min_int64(<4 x i64>) nounwind readnone {
|
||||
reduce4(i64, @__min_varying_int64, @__min_uniform_int64)
|
||||
}
|
||||
|
||||
define internal i64 @__reduce_max_int64(<4 x i64>) nounwind readnone {
|
||||
reduce4(i64, @__max_varying_int64, @__max_uniform_int64)
|
||||
}
|
||||
|
||||
define internal i64 @__reduce_min_uint64(<4 x i64>) nounwind readnone {
|
||||
reduce4(i64, @__min_varying_uint64, @__min_uniform_uint64)
|
||||
}
|
||||
|
||||
define internal i64 @__reduce_max_uint64(<4 x i64>) nounwind readnone {
|
||||
reduce4(i64, @__max_varying_uint64, @__max_uniform_uint64)
|
||||
}
|
||||
|
||||
reduce_equal(4)
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; masked store
|
||||
|
||||
@@ -298,3 +432,41 @@ define void @__masked_store_blend_64(<4 x i64>* nocapture %ptr, <4 x i64> %new,
|
||||
store <4 x i64> %final, <4 x i64> * %ptr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; masked store
|
||||
|
||||
masked_store_blend_8_16_by_4()
|
||||
|
||||
gen_masked_store(4, i8, 8)
|
||||
gen_masked_store(4, i16, 16)
|
||||
gen_masked_store(4, i32, 32)
|
||||
gen_masked_store(4, i64, 64)
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; unaligned loads/loads+broadcasts
|
||||
|
||||
load_and_broadcast(4, i8, 8)
|
||||
load_and_broadcast(4, i16, 16)
|
||||
load_and_broadcast(4, i32, 32)
|
||||
load_and_broadcast(4, i64, 64)
|
||||
|
||||
load_masked(4, i8, 8, 1)
|
||||
load_masked(4, i16, 16, 2)
|
||||
load_masked(4, i32, 32, 4)
|
||||
load_masked(4, i64, 64, 8)
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; gather/scatter
|
||||
|
||||
; define these with the macros from stdlib.m4
|
||||
|
||||
gen_gather(4, i8)
|
||||
gen_gather(4, i16)
|
||||
gen_gather(4, i32)
|
||||
gen_gather(4, i64)
|
||||
|
||||
gen_scatter(4, i8)
|
||||
gen_scatter(4, i16)
|
||||
gen_scatter(4, i32)
|
||||
gen_scatter(4, i64)
|
||||
|
||||
Reference in New Issue
Block a user