diff --git a/docs/ReleaseNotes.txt b/docs/ReleaseNotes.txt
index d09c2b80..a0e2c24f 100644
--- a/docs/ReleaseNotes.txt
+++ b/docs/ReleaseNotes.txt
@@ -7,8 +7,9 @@ of small bugs have been fixed.
 
 New targets:
 
-* This release provides "beta" support for compiling to Intel Xeon Phi (the
-  "Many Integrated Core" arthiecture).  See
+* This release provides "beta" support for compiling to Intel® Xeon
+  Phi™ processor, code named Knights Corner, the first processor in
+  the Intel® Many Integrated Core Architecture.  See
   http://ispc.github.com/ispc.html#compiling-for-the-intel-xeon-phi-architecture
   for more details on this support.
 
diff --git a/docs/ispc.rst b/docs/ispc.rst
index 6894a520..d3ed6344 100644
--- a/docs/ispc.rst
+++ b/docs/ispc.rst
@@ -59,7 +59,7 @@ Contents:
   + `Basic Command-line Options`_
   + `Selecting The Compilation Target`_
   + `Generating Generic C++ Output`_
-  + `Compiling For The Intel Xeon Phi Architecture`_
+  + `Compiling For The Intel® Many Integrated Core Architecture`_
   + `Selecting 32 or 64 Bit Addressing`_
   + `The Preprocessor`_
   + `Debugging`_
@@ -560,14 +560,16 @@ C++ file; this can be used to easily include specific implementations of
 the vector types and functions.
 
 
-Compiling For The Intel Xeon Phi Architecture
----------------------------------------------
+Compiling For The Intel® Many Integrated Core Architecture
+----------------------------------------------------------
 
-``ispc`` has beta-level support for compiling for the many-core Intel® Xeon
-Phi architecture (formerly, "Many Integrated Cores" / MIC.)  This support
-is based on the "generic" C++ output, described in the previous section.
+``ispc`` has beta-level support for compiling for the many-core Intel®
+Xeon Phi™ processor, part of the Intel® Many Integrated Core
+Architecture (MIC).  For the first generation of processor, code named
+Knights Corner, this support is based on the "generic" C++ output,
+described in the previous section.
 
-To compile for Xeon Phi, first generate intermediate C++ code:
+To compile for Knight's Corner, first generate intermediate C++ code:
 
 ::
 
@@ -575,19 +577,19 @@ To compile for Xeon Phi, first generate intermediate C++ code:
       --c++-include-file=knc.h
 
 The ``ispc`` distribution now includes a header file,
-``examples/intrinsics/knc.h``, which maps from the generic C++ output to
-the corresponding intrinsic operations for Intel Xeon Phi.  Thus, to
-generate an object file, use the Intel C Compiler (``icc``) compile the C++
-code generated by ``ispc``, setting the ``#include`` search path so that it
-can find the ``examples/intrinsics/knc.h`` header file in the ``ispc``
-distribution.
+``examples/intrinsics/knc.h``, which maps from the generic C++ output
+to the corresponding intrinsic operations supported by Knights Corner.  Thus,
+to generate an object file, use the Intel C Compiler (``icc``) compile
+the C++ code generated by ``ispc``, setting the ``#include`` search
+path so that it can find the ``examples/intrinsics/knc.h`` header file
+in the ``ispc`` distribution.
 
 ::
 
   icc -mmic -Iexamples/intrinsics/ foo.cpp -o foo.o 
 
 With the current beta implementation, complex ``ispc`` programs are able to
-run on Xeon Phi, though there are a number of known limitations:
+run on Knights Corner, though there are a number of known limitations:
 
 * The ``examples/intrinsics/knc.h`` header file isn't complete yet; for
   example, vector operations with ``int8`` and ``int16`` types aren't yet
@@ -597,8 +599,9 @@ run on Xeon Phi, though there are a number of known limitations:
 
 * If you use the ``launch`` functionality to launch tasks across cores,
   note that the pthreads task system implemented in
-  ``examples/tasksys.cpp`` hasn't been tuned for Xeon Phi yet, and has
-  known issues with setting thread affinities optimally.
+  ``examples/tasksys.cpp`` offers several implemenetations for Knights
+  Corner.  You will need to experiment to understand which one is most
+  appropriate for your workload.
 
 * The compiler currently emits unaligned memory accesses in many cases
   where the memory address is actually aligned.  This may unnecessarily
@@ -617,12 +620,13 @@ run on Xeon Phi, though there are a number of known limitations:
 All of these issues are currently actively being addressed and will be
 fixed in future releases.
 
-If you do use the current version of ``ispc`` on Xeon Phi, please let us
-know of any bugs or unexpected results.  (Also, any interesting results!).
-*Note that access to Xeon Phi and public discussion of Xeon Phi performance
-is still governed by NDA*, so please send email to "matt dot pharr at intel
-dot com" for any issues that shouldn't be filed in the `public ispc bug
-tracker`_.
+If you do use the current version of ``ispc`` on Knights Corner,
+please let us know of any bugs or unexpected results.  (Also, any
+interesting results!).  *Note that access to Intel® Xeon Phi™
+processor and public discussion of Intel® Xeon Phi™ processor
+performance is still governed by NDA*, so please send email to "matt
+dot pharr at intel dot com" for any issues that shouldn't be filed in
+the `public ispc bug tracker`_.
 
 .. _public ispc bug tracker: https://github.com/ispc/ispc/issues